Abstract: A method of fabricating a MOS capacitor in a complementary MOS fabrication process with dual-doped poly gates comprises providing a substrate of a first conductive type, the substrate having a first well of the first conductive type and a second well of a second conductive type. A dielectric layer is formed on the substrate. A first poly gate of the first conductive type is formed on the dielectric layer over the first well and a second poly gate of the second conductive type is formed on the dielectric layer over the second well. A first doped region of the first conductive type is formed in the substrate at each side of the first poly gate. A second doped region of the second conductive type is formed in the substrate at each side of the second poly gate layer. A spacer is formed on sidewalls of the first poly gate and the second poly gate, wherein a portion of the dielectric layer is also removed to expose a portion of the first doped region and a portion of the second doped region.

Abstract: An integrated radio frequency receiver, having a local oscillator, a mixer apparatus, a phase-shift apparatus, and an analog-to-digital conversion apparatus. The local oscillator is used to generate a local oscillation signal. The mixer mixes, filters and amplifies a radio-frequency carrier input signal and the local oscillation signal to output the first amplified and second amplified signals. The phases of the first and second amplified signals are shifted with first and second degrees as first and second output phase-shifted signals, respectively. The analog-to-digital conversion apparatus then performs analog-to-digital conversion on the first amplified and the second phase-shifted signal, and the second amplified and first phase-shifted signal to output an in-phase signal and an orthogonal-phase signal, respectively.

Abstract: A method of fabricating a MOS capacitor in a complementary MOS fabrication process with dual-doped poly gates comprises providing a substrate of a first conductive type, the substrate having a first well of the first conductive type and a second well of a second conductive type. A dielectric layer is formed on the substrate. A first poly gate of the first conductive type is formed on the dielectric layer over the first well and a second poly gate of the second conductive type is formed on the dielectric layer over the second well. A first doped region of the first conductive type is formed in the substrate at each side of the first poly gate. A second doped region of the second conductive type is formed in the substrate at each side of the second poly gate layer. A spacer is formed on sidewalls of the first poly gate and the second poly gate, wherein a portion of the dielectric layer is also removed to expose a portion of the first doped region and a portion of the second doped region.

Abstract: A communications device for transmitting RF signals from an external antenna. The device comprises a transceiver that sends signals over a cable to an external active antenna. In one embodiment the signals transmitted over the cable intermediate RF frequency signals. The active antenna receives the intermediate RF signals over the cable and up converts or down converts the respective RF transmit and receive signals. In another embodiment of the invention the signals transmitted over the cable are digital signals. The active antenna is functional to process, and covert the respective RF transmit and receive signals.

Abstract: A fuse structure in a semiconductor device and a manufacturing method thereof. The fuse structure includes a insulation layer, a metal layer on a top surface of the first insulation layer, the metal layer having a middle portion narrower than a first and a second outer portions of the metal layer, a second insulation layer over the metal layer, a first top metal layer and a second top metal layer on a top surface of the second insulation layer and a plurality of vias connecting the first and second top metal layers with the metal layer respectively. The first top metal layer is connected to the first outer portion of the metal layer and the second top metal layer is connected to the second outer portion of the metal layer. The middle portion is disposed between the first and second outer portions of the metal layer.

Abstract: A computer peripheral point device with a power generating means that allows for extended lifetime of a devices batteries. The present invention discloses an apparatus wherein a generator is driven by the rotation of a mouse ball through an adjacent roller. In another embodiment the downward force of “clicking” the mouse is converted into electrical energy through a piezoelectric generator. In another embodiment of the invention an eccentric mass generator converts the kinetic energy from the movement of the mouse into electrical energy. In yet another embodiment a plurality of solar cells are placed on the external surface of a point device converting available light into electrical energy.

Abstract: The present invention provides an integrated inductor device having a high Q value, a low stray capacitance, and a small area that are compatible with conventional RF CMOS process. The inductor device has a plurality of conductive paths collocated in the same space for each gate, drain, and source of a RF transistor. The conductive paths are formed as a square-loop with 90 degrees turns with a space between adjacent conductive paths. Wherein the conductive paths are formed inside while staying geometrically parallel to each other. The adjacent conductive path carries a current in the same direction so all the conductive paths give positive contribution to a total magnetic flux.

Abstract: A method of fabricating a MOS capacitor in a complementary MOS fabrication process with dual-doped poly gates comprises providing a substrate of a first conductive type, the substrate having a first well of the first conductive type and a second well of a second conductive type. A dielectric layer is formed on the substrate. A first poly gate of the first conductive type is formed on the dielectric layer over the first well and a second poly gate of the second conductive type is formed on the dielectric layer over the second well. A first doped region of the first conductive type is formed in the substrate at each side of the first poly gate. A second doped region of the second conductive type is formed in the substrate at each side of the second poly gate layer. A spacer is formed on sidewalls of the first poly gate and the second poly gate, wherein a portion of the dielectric layer is also removed to expose a portion of the first doped region and a portion of the second doped region.

Abstract: A method of fabricating a MOS capacitor in a complementary MOS fabrication process with dual-doped poly gates comprises providing a substrate of a first conductive type, the substrate having a first well of the first conductive type and a second well of a second conductive type. A dielectric layer is formed on the substrate. A first poly gate of the first conductive type is formed on the dielectric layer over the first well and a second poly gate of the second conductive type is formed on the dielectric layer over the second well. A first doped region of the first conductive type is formed in the substrate at each side of the first poly gate. A second doped region of the second conductive type is formed in the substrate at each side of the second poly gate layer. A spacer is formed on sidewalls of the first poly gate and the second poly gate, wherein a portion of the dielectric layer is also removed to expose a portion of the first doped region and a portion of the second doped region.

Abstract: A method of fabricating an interconnect of a capacitor. A substrate having a capacitor is provided. The capacitor comprises a bottom electrode electrically connected to the substrate, a dielectric layer and a top electrode thereon. A spin-on dielectric layer is formed on the substrate and the capacitor. The spin-on dielectric layer on the substrate is thicker than that on the top electrode. The spin-on dielectric layer is etched back until the top electrode is exposed. A patterned metal layer is formed on the spin-on dielectric layer and the top electrode with a bottom surface in directly contact with a top surface of the top electrode.

Abstract: A method of fabricating an interconnect of a capacitor. A substrate having a capacitor is provided. The capacitor comprises a bottom electrode electrically connected to the substrate, a dielectric layer and a top electrode thereon. A spin-on dielectric layer is formed on the substrate and the capacitor. The spin-on dielectric layer on the substrate is thicker than that on the top electrode. The spin-on dielectric layer is etched back until the top electrode is exposed. A patterned metal layer is formed on the spin-on dielectric layer and the top electrode with a bottom surface in directly contact with a top surface of the top electrode.

Abstract: A method for manufacturing an inductor. A silicon substrate of a first conductive type is provided. A spiral conductive layer is formed over the silicon substrate. A doped region of a second conductive type is formed in the substrate below the spiral conductive layer. A doped region of the first conductive type is next formed in the substrate around the doped region of the second conductive type. A reverse-bias voltage is applied to the doped region of the first conductive type and the doped region of the second conductive type. The application of a reverse-bias voltage creates a depletion region beneath the doped region of the second conductive type and the space between the doped regions.

Abstract: An inductor. A silicon substrate of a first conductive type is provided. A spiral conductive layer is formed over the silicon substrate. A doped region of a second conductive type is formed in the substrate below the spiral conductive layer. A doped region of the first conductive type is next formed in the substrate around the doped region of the second conductive type. A reverse-bias voltage is applied to the doped region of the first conductive type and the doped region of the second conductive type. The application of a reverse-bias voltage creates a depletion region beneath the doped region of the second conductive type and the space between the doped regions.

Abstract: A method for manufacturing an inductor. A silicon substrate of a first conductive type is provided. A spiral conductive layer is formed over the silicon substrate. A doped region of a second conductive type is formed in the substrate below the spiral conductive layer. A doped region of the first conductive type is next formed in the substrate around the doped region of the second conductive type. A reverse-bias voltage is applied to the doped region of the first conductive type and the doped region of the second conductive type. The application of a reverse-bias voltage creates a depletion region beneath the doped region of the second conductive type and the space between the doped regions.

Abstract: An antenna is provided including first and second strip resonant elements, a dielectric and a metal cover. The first strip resonant element has an F-shaped area that lies in a first plane. The second strip resonant element has an L-shaped area that lies in a second plane that is parallel to the first plane. The second strip at least partially underlies the first strip. The dielectric is positioned between the first and second strips. A metal cover is provided. Part of the metal cover is positioned perpendicularly to the first and second strips so as to provide electromagnetic shielding for the first and second strips.