Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: The disclosure provides an electronic device including a host control circuit, a display driving circuit, a touch driving circuit and a logic circuit. The host control circuit is configured to provide a first reset control signal. The display driving circuit is configured to reset according to the first reset control signal. The logic circuit is configured to generate a second reset control signal to the touch driving circuit according to the first reset control signal and an enable signal. During a sleep mode of the electronic device, the enable signal has a first logic level. In response to the enable signal at the first logic level, the logic circuit generates the second reset control signal at the first logic level. The touch driving circuit does not reset according to the second reset control signal at the first logic level.

Abstract: A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.

Abstract: A semiconductor device is provided. The semiconductor device includes a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; an active region between the second semiconductor layer and the first semiconductor layer; an electron blocking structure between the active region and the second semiconductor layer; a first nitride semiconductor layer between the active region and the electron blocking structure; and a second nitride semiconductor layer between the electron blocking structure and the second semiconductor layer. The first nitride semiconductor layer includes a first indium content, a first aluminum content and a first conductivity-type dopant. The second nitride semiconductor layer includes a second indium content, a second aluminum content and a second conductivity-type dopant.

Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.

Abstract: A wearable device includes a conducting frame, a circuit board, and a grounding member. The conducting frame includes a first part and a second part that are separated. The circuit board has a system grounding surface and is disposed inside the conducting frame. The grounding member is disposed inside the conducting frame and connected to the first part. The first part and the grounding member are formed as a first antenna. The first part has a first feeding terminal. The grounding member has a first grounding terminal, and the first grounding terminal is connected to the system grounding surface of the circuit board. The second part is formed as a second antenna. The second antenna has a second feeding terminal, a second grounding terminal, and a third grounding terminal. The second and the third grounding terminals are connected to the system grounding surface of the circuit board.

Abstract: A method of forming an image sensor includes forming a photodiode within a semiconductor substrate. The method further includes disposing an interconnect structure over the semiconductor substrate. The interconnect structure includes a contact etch stop layer (CESL) over the photodiode; and a plurality of dielectric layers over the CESL, wherein at least one dielectric layer of the plurality of dielectric layers comprises a low dielectric constant (low-k) material. The method further includes patterning at least the plurality of dielectric layers, wherein patterning at least the plurality of dielectric layers comprises defining an opening above an active region of the photodiode. The method further includes depositing a cap layer on sidewalls of the opening, wherein the cap layer includes a dielectric material having a higher moisture resistance than the low-k dielectric material.

Abstract: A system and a method for parameter optimization with adaptive search space and a user interface using the same are provided. The system includes a data acquisition unit, an adaptive adjustment unit and an optimization search unit. The data acquisition unit obtains a set of executed values of several operating parameters and a target parameter. The adaptive adjustment unit includes a parameter space transformer and a search range definer. The parameter space transformer performs a space transformation on a parameter space of the operating parameters according to the executed values. The search range definer defines a parameter search range in a transformed parameter space based on the sets of the executed values. The optimization search unit takes the parameter search range as a limiting condition and takes optimizing the target parameter as a target to search for a set of recommended values of the operating parameters.

Abstract: A media docking device includes an input module, an output module and a processing module. The input module is electrically connected to a media source device for receiving media data. The output module is electrically connected to a media play device. The processing module determines if an instruction is received from the media source device or a remote device. If the instruction is not received, the processing module transfers the media data to the output module to transmit to the media play device. If the instruction is received, the processing module limits a transmission of the media data according to the instruction, such that the media data will not be completely played by the media play device.

Abstract: A media docking device includes an input circuit, an output circuit and a processing circuit. The input circuit is electrically connected to a media source device for receiving media data. The output circuit is electrically connected to a media play device. The processing circuit is electrically connected to the input circuit and the output circuit. The processing circuit determines if a verification procedure is passed. If the verification procedure is passed, the processing circuit transfers the media data to the media play device. If the verification procedure is not passed, the processing circuit limits a transmission of the media data, such that the media data will not be completely played by the media play device.

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: An IC structure includes a fin structure, a contact overlying the fin structure along a first direction, and an isolation layer between the contact and the fin structure. The isolation layer is adjacent to a portion of the contact along a second direction perpendicular to the first direction.

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, a plasma process combining etching and deposition processes is used to form a recess having a rounded corner shape in a cross section along the second direction.

Abstract: An optical detection device includes a first linear light source, a second linear light source, an optical sensor array and a processor. The first linear light source is adapted to project a first long strip illumination beam onto the target container. The second linear light source is adapted to project a second long strip illumination beam onto the target container, and the second long strip illumination beam is crossed with the first long strip illumination beam. The optical sensor array is adapted to receive a first long strip detection beam and a second long strip detection beam reflected from the target container. The processor is electrically connected to the optical sensor array. The processor is adapted to analyze intensity distribution of the first long strip detection beam and the second long strip detection beam to acquire a relative distance between the optical sensor array and the target container.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: The present disclosure provides a semiconductor structure including a base layer, a first conductive line disposed on the base layer, a first dielectric pillar disposed on the base layer, a second dielectric pillar disposed on the base layer, a first liner, and a second liner. The first conductive line is disposed between the first dielectric pillar and the second dielectric pillar. The first liner encloses a first air gap, and is disposed between the first dielectric pillar and the first conductive line. The second liner encloses a second air gap, and is disposed between the second dielectric pillar and the first conductive line.

Abstract: A touch display and a sensing method are provided. The touch display includes a substrate, a display array disposed on the substrate and having an upper layer which includes a shielding metal layer, a touch sensor disposed above the display array, and a controller coupled to the display array and the touch sensor. The controller is configured to enable the display array to display and obtain a first sensing result from the touch sensor during a first time interval, and disable the display array and obtain a second sensing result from the touch sensor during a second time interval. According to the first sensing result and the second sensing result, a touch determination result of whether the touch display receives a touch from a user is generated.

Abstract: A method for additive manufacturing is provided, including: mixing a hardener with a sand material, so that the hardener is evenly coated on a surface of the sand material, and then spraying a binder through a nozzle, reacting the binder sprayed through the nozzle with the surface of the sand material evenly coated with the hardener to harden a sand mold. Therefore, the problem of nozzle clogging may be overcome, and a solid with a particle size of less than 0.6 ?m may be obtained by the additive manufacturing. In addition, the hardening speed can be adjusted according to the size of the sand mold. Compared with a general sand mold product, the hardening speed may be increased and the storage life of the binder may be prolonged when the sand mold has a large size.

Abstract: An ultra-wideband assisted precise positioning system and an ultra-wideband assisted precise positioning method are provided. The method includes: arranging a plurality of device nodes in a target area; configuring a central control device node to communicatively connect to the device nodes; configuring the device nodes to perform a positioning process to obtain measured distances and positioning positions to be corrected; and configuring a central control processor to execute a positioning algorithm. The positioning algorithm includes: obtaining the measured distances and the positioning positions to be corrected; for each of the positioning positions to be corrected, performing a center-of-gravity weighting processing on neighboring points for obtaining initial guess positions; and obtaining the initial guess positions to input to an optimizer and optimize an objective function, and finding corrected positions with relatively smallest errors.