Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: A system and method for reducing thermal transfer in a dual ampoule system. The dual ampoule system includes a first ampoule, a second ampoule, and a planar heat shield. The planar heat shield is positioned between the first ampoule and the second ampoule, where the planar heat shield is configured to resist thermal transfer between the first ampoule and the second ampoule.

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.

Abstract: A driving method of cholesteric liquid crystal display is provided. A liquid crystal driving unit is used to output row driving voltage to multiple row circuit structures. Sequentially column driving voltage is outputted to multiple column circuit structures in a scanning manner. Scanning a column circuit structure takes one scanning time sequence. When starting the Nth time sequence of pixels to present the image, a ghost elimination voltage is applied to eliminate the image of the Mth time sequence and present it at the image position of the Nth time sequence, where M=N+1 and the ghost elimination voltage is applied at T. By doing so, the phenomenon of ghosts appearing on cholesteric liquid crystal displays can be improved, and the imaging quality of cholesteric liquid crystal displays can be improved.

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. The metal-containing layer and the silicon-containing layer in combination act as a work-function layer. A planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer forming a gate stack.

Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.

Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

Abstract: Various techniques pertaining to non-coherent noise reduction for audio enhancement on a multi-microphone mobile device are proposed. A processor receives a plurality of signals from a plurality of audio sensors corresponding to a plurality of channels responsive to sensing by the plurality of audio sensors. The processor then performs a non-coherent noise reduction on one or more signals of the plurality of signals to suppress one or more non-coherent noises in each of the one or more signals based on a respective signal-to-noise ratio (SNR) associated with each of the one or more signals. The processor further combines the plurality of signals subsequent the noise reduction to generate an output signal.

Abstract: The invention provides a display device. The display device includes a display unit and a processing unit. The processing unit is coupled to the display unit. The processing unit provides a user interface through the display unit to prompt a user to adjust at least one response effect. The processing unit presents an image quality checking animation through the display unit or the user interface. The processing unit reflects an adjustment of the response effect in the image quality checking animation in real time.

Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Abstract: An information handling system detects an initial insertion of an alternating current (AC) adapter, and determines an identifier associated with the AC adapter. The system may also determine a parameter for attenuating noise generated by the AC adapter based on the identifier, and attenuate the noise generated by the AC adapter by applying the parameter.

Abstract: A method includes: forming overlay structures at scribe lines of a wafer, each side of a die region of the wafer is disposed with at least one of the overlay structures, each of the overlay structures comprises at least one feature and at least one recess disposed above the feature, the feature and the recess are respectively disposed at a first and second layers of the wafer, the recess exposes a portion of the feature vertically aligned with the recess; acquiring an image of the overlay structures; measuring a first dimension and a second dimension of a first portion and a second portion of the recess, respectively; determining an overlay between the first and second layers of an edge region of the wafer based on an average of differences between the first and second dimensions; and modifying a subsequent lithography step to compensate for the overlay.

Abstract: A method includes: forming overlay structures at scribe lines of a wafer, each side of a die region of the wafer is disposed with at least one of the overlay structures, each of the overlay structures comprises at least one feature and at least one recess disposed above the feature, the feature and the recess are respectively disposed at a first and second layers of the wafer, the recess exposes a portion of the feature vertically aligned with the recess; acquiring an image of the overlay structures; measuring a first dimension and a second dimension of a first portion and a second portion of the recess, respectively; determining an overlay between the first and second layers of an edge region of the wafer based on an average of differences between the first and second dimensions; and modifying a subsequent lithography step to compensate for the overlay.

Abstract: The present invention discloses a compact sensor package structure, which comprises a package body, an LED chip and a sensor chip. The package body has a first room, a second room, a first hole and a second hole. The first and second rooms are independent to each other. The first and second holes interconnect the interiors and the external environments of the first and second rooms. The LED chip is arranged inside the first room, corresponding to the first hole and below the first hole. The LED chip projects light through the first hole. The sensor chip is arranged inside the second room, corresponding to the second hole and above/below the second hole. The sensor chip receives light via the second hole. The present invention features two independent rooms for two chips and prevents interference between the two chips.

Abstract: A method and apparatus for detecting the added functions of a telephone dialer by adding diodes to the IC circuit and using as part of the input pins such that the need for total number of input pins and thus the manufacturing costs of the IC are reduced. The method is executed by using the available keyboard input/output boards without increasing the need for extra input pins in order to detect whether there is any diode in existence that is connected among the input/output ports.