Patents by Inventor Chi-Chang Wu

Chi-Chang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10790205
    Abstract: A method includes: forming overlay structures at scribe lines of a wafer, each side of a die region of the wafer is disposed with at least one of the overlay structures, each of the overlay structures comprises at least one feature and at least one recess disposed above the feature, the feature and the recess are respectively disposed at a first and second layers of the wafer, the recess exposes a portion of the feature vertically aligned with the recess; acquiring an image of the overlay structures; measuring a first dimension and a second dimension of a first portion and a second portion of the recess, respectively; determining an overlay between the first and second layers of an edge region of the wafer based on an average of differences between the first and second dimensions; and modifying a subsequent lithography step to compensate for the overlay.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Pin Chen, Te-Chia Ku, Chien-Kwen Chen, Chi-Chang Wu, Cheng-Ming Ho
  • Publication number: 20200105629
    Abstract: A method includes: forming overlay structures at scribe lines of a wafer, each side of a die region of the wafer is disposed with at least one of the overlay structures, each of the overlay structures comprises at least one feature and at least one recess disposed above the feature, the feature and the recess are respectively disposed at a first and second layers of the wafer, the recess exposes a portion of the feature vertically aligned with the recess; acquiring an image of the overlay structures; measuring a first dimension and a second dimension of a first portion and a second portion of the recess, respectively; determining an overlay between the first and second layers of an edge region of the wafer based on an average of differences between the first and second dimensions; and modifying a subsequent lithography step to compensate for the overlay.
    Type: Application
    Filed: January 10, 2019
    Publication date: April 2, 2020
    Inventors: Feng-Pin CHEN, Te-Chia KU, Chien-Kwen CHEN, Chi-Chang WU, Cheng-Ming HO
  • Publication number: 20120025211
    Abstract: The present invention discloses a compact sensor package structure, which comprises a package body, an LED chip and a sensor chip. The package body has a first room, a second room, a first hole and a second hole. The first and second rooms are independent to each other. The first and second holes interconnect the interiors and the external environments of the first and second rooms. The LED chip is arranged inside the first room, corresponding to the first hole and below the first hole. The LED chip projects light through the first hole. The sensor chip is arranged inside the second room, corresponding to the second hole and above/below the second hole. The sensor chip receives light via the second hole. The present invention features two independent rooms for two chips and prevents interference between the two chips.
    Type: Application
    Filed: July 6, 2011
    Publication date: February 2, 2012
    Applicant: SIGURD MICROELECTRONICS CORP.
    Inventors: TSAN-LIEN YEH, WAN-HUA WU, SZU-CHUAN PANG, CHI-CHANG WU, MING-HUNG HUNG
  • Patent number: 5541989
    Abstract: A method and apparatus for detecting the added functions of a telephone dialer by adding diodes to the IC circuit and using as part of the input pins such that the need for total number of input pins and thus the manufacturing costs of the IC are reduced. The method is executed by using the available keyboard input/output boards without increasing the need for extra input pins in order to detect whether there is any diode in existence that is connected among the input/output ports.
    Type: Grant
    Filed: October 24, 1994
    Date of Patent: July 30, 1996
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Chang Wu, Dune-Fung Hsiou
  • Patent number: D511896
    Type: Grant
    Filed: March 17, 2004
    Date of Patent: November 29, 2005
    Inventor: Chi-Chang Wu
  • Patent number: D500177
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: December 21, 2004
    Inventor: Chi Chang Wu