Patents by Inventor Chi-Chao Tseng

Chi-Chao Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7718078
    Abstract: A manufacturing method of a circuit board is provided. Firstly, a substrate board having a plurality of through holes is provided. Next, a first metal layer is electro-less plated on the surface of the substrate board and the surface of the through holes. Then, a second metal layer is plated on the first metal layer. After that, the second metal layer and the first metal layer are patterned to form a patterned circuit layer. Lastly, a third metal layer is plated on the patterned circuit layer.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: May 18, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi-Chao Tseng, Ming-Loung Lu
  • Patent number: 7504282
    Abstract: A method of manufacturing a substrate for packaging ICs is disclosed, which coats a thin conductive layer on the bottom surface of the laminated circuit board, for electrically connecting the pad and the circuit pattern formed on the bottom surface after one line photolithography/etching step. The pad formed on the top surface of the laminated circuit board can be electrically connected to the power applied in the electroplating process through the electroplating layer in the through hole and the conductive layer. Hence, the times of line photolithography/etching steps required for the prior process can be reduced, thereby solving the issues of lowering yield caused by the line photolithography/etching steps.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: March 17, 2009
    Assignee: ASE (Shanghai) Inc.
    Inventor: Chi-Chao Tseng
  • Publication number: 20070287285
    Abstract: A manufacturing method of a circuit board is provided. Firstly, a substrate board having a plurality of through holes is provided. Next, a first metal layer is electro-less plated on the surface of the substrate board and the surface of the through holes. Then, a second metal layer is plated on the first metal layer. After that, the second metal layer and the first metal layer are patterned to form a patterned circuit layer. Lastly, a third metal layer is plated on the patterned circuit layer.
    Type: Application
    Filed: September 14, 2006
    Publication date: December 13, 2007
    Inventors: Chi-Chao Tseng, Ming-Loung Lu
  • Publication number: 20070264750
    Abstract: A method of manufacturing a substrate for packaging ICs is disclosed, which coats a thin conductive layer on the bottom surface of the laminated circuit board, for electrically connecting the pad and the circuit pattern formed on the bottom surface after one line photolithography/etching step. The pad formed on the top surface of the laminated circuit board can be electrically connected to the power applied in the electroplating process through the electroplating layer in the through hole and the conductive layer. Hence, the times of line photolithography/etching steps required for the prior process can be reduced, thereby solving the issues of lowering yield caused by the line photolithography/etching steps.
    Type: Application
    Filed: November 28, 2006
    Publication date: November 15, 2007
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventor: Chi-Chao Tseng