Patents by Inventor CHI-CHE WU

CHI-CHE WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12656395
    Abstract: A circuit screening system including a target circuit under test receiving a first testing signal in a first period and a second testing signal in a second period; and a clock generating circuit providing a clock signal to the target circuit under test, the clock signal triggering the target circuit under test to receive the first testing signal in the first period and the second testing signal in the second period; the clock signal having a first profile and a second profile in the first period and the second period, respectively, and the first profile and the second profile having a phase difference.
    Type: Grant
    Filed: November 24, 2023
    Date of Patent: June 16, 2026
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Che Wu, Tsung-Yang Hung, Jia-Ming Guo, Yi-Na Fang, Ming-Yih Wang
  • Publication number: 20260100575
    Abstract: A connection interface for a source device may include switching circuitry for causing the source device to deliver electrical energy to a sink device via an output of the source device when the source device and the sink device are electrically coupled via a connection, discharge circuitry for discharging an output voltage on the output when the connection is disconnected, and control circuitry for causing the switching circuitry to be activated and the discharge circuitry to be deactivated when the source device and the sink device are electrically coupled via the connection and causing the switching circuitry to be deactivated and the discharge circuitry to be activated when the connection is disconnected.
    Type: Application
    Filed: October 8, 2024
    Publication date: April 9, 2026
    Applicant: Dell Products L.P.
    Inventors: Wei-Cheng YU, Merle J. WOOD, III, Chin-Jui LIU, Chi-Che WU, Chia-Jung TSAI
  • Publication number: 20260064170
    Abstract: A device for receiving power from a power supply and providing power to an information handling system including an embedded controller configured to monitor a load condition for the power supplied to the information handling system and regulate an output voltage of a power supply to maintain the output voltage supplied to the information handling system within a tolerance.
    Type: Application
    Filed: August 30, 2024
    Publication date: March 5, 2026
    Inventors: Wei-Cheng Yu, Merle Jackson Wood, III, Chi-Che Wu, Chin-Jui Liu
  • Patent number: 12541236
    Abstract: Systems and methods that may be implemented to determine electrical characteristic/s of one or more power supply cable/s that are coupled to supply power from a power supply to a battery-powered information handling system, and to take one or more actions based on the determined electrical characteristic/s. The disclosed systems and methods may be so implemented to detect values of input voltage and input current that are provided from the power supply cable to a battery-powered information handling system, and to take one or more actions based on these detected values of input voltage and input current, such as power supply voltage compensation, protection of the power supply, alerts to the battery-powered information handling system, and/or warnings to a user of the battery-powered information handling system.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: February 3, 2026
    Assignee: Dell Products L.P.
    Inventors: Merle Wood, III, Chin-Jui Liu, Chi-Che Wu, Tsung-Cheng Liao, Wei-Cheng Yu
  • Patent number: 12413091
    Abstract: A power adaptor provides power from a power source to a load device. The power adaptor includes a bulk capacitor and a controller. The controller detects a voltage level of input power from the power source, charges the bulk capacitor, detects a distortion of the voltage level in response to charging the bulk capacitor, and sets an output power limit for the power adaptor from a maximum output power limit for the power adaptor to a reduced output power limit in response to detecting the distortion.
    Type: Grant
    Filed: April 24, 2024
    Date of Patent: September 9, 2025
    Assignee: Dell Products L.P.
    Inventors: Geroncio O. Tan, Wei-Cheng Yu, Chi-Che Wu
  • Publication number: 20250238059
    Abstract: An information handling system includes first and second USB-C channels and a baseboard management controller (BMC). The first USB-C channel receives power from a first power adaptor, and the second USB-C channel receives power from a second power adaptor. The BMC determines an average current delivered to the information handling system from the first power adaptor and the second power adaptor, allocates a first portion of the average current to the first power adaptor and a second portion of the average current to the second power adaptor, and directs the first power adaptor to provide the first portion of the average current and the second power adaptor to provide the second portion of the average current.
    Type: Application
    Filed: January 22, 2024
    Publication date: July 24, 2025
    Inventors: Wei-Cheng Yu, Merle Jackson Wood, III, Chin Jui Liu, Chi-Che Wu, Wen-Yung Chang
  • Patent number: 12248022
    Abstract: An apparatus for testing a device under test (DUT) is provided. The apparatus includes a power supply device and a data generating device. The power supply device is configured to provide a first voltage and a second voltage to the DUT. The data generating device is configured to provide first data to the DUT. The power supply device is configured to provide the first voltage to the DUT in a first time duration. The data generating device is configured to provide the first data to the DUT in the first time duration. The power supply device is configured to provide the second voltage to the DUT in a second time duration after the first time duration. The second voltage is different from the first voltage.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: March 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Che Wu, Tsung-Yang Hung, Ming-Yih Wang, Jia-Ming Guo
  • Publication number: 20250079852
    Abstract: A power adapter includes a flyback converter and a buck converter. If a first device is a preferred device, then power is allocated to the first device up to a first value. If a second device is plugged in, then power is re-allocating to the first device up to a second value and up to a third value to the second device. A total of the second value and the third value is up to the first value.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 6, 2025
    Inventors: Tsung-Cheng Liao, Wei-Cheng Yu, Merle Jackson Wood III, Chin Jui Liu, Tun-Chieh Liang, Chi-Che Wu
  • Patent number: 12174682
    Abstract: An information handling system detects an initial insertion of an alternating current (AC) adapter, and determines an identifier associated with the AC adapter. The system may also determine a parameter for attenuating noise generated by the AC adapter based on the identifier, and attenuate the noise generated by the AC adapter by applying the parameter.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: December 24, 2024
    Assignee: Dell Products L.P.
    Inventors: Chi-Che Wu, Wei-Cheng Yu, Geroncio Ong Tan, Tsung-Cheng Liao, Henry Chang
  • Publication number: 20240264654
    Abstract: An information handling system detects an initial insertion of an alternating current (AC) adapter, and determines an identifier associated with the AC adapter. The system may also determine a parameter for attenuating noise generated by the AC adapter based on the identifier, and attenuate the noise generated by the AC adapter by applying the parameter.
    Type: Application
    Filed: February 6, 2023
    Publication date: August 8, 2024
    Inventors: Chi-Che Wu, Wei-Cheng Yu, Geroncio Ong Tan, Tsung-Cheng Liao, Henry Chang
  • Patent number: 12007438
    Abstract: A method is provided and includes several operations: testing multiple scan chains in multiple shift cycles to obtain multiple values; determining at least one fail chain in the scan chains and determining at least one fail shift cycle corresponding to at least one fail value in the values; mapping the at least one fail chain and the at least one fail shift cycle to the scan chains to identify the at least one fail flip flop; and identifying at least one fault site corresponding to the at least one fail flip flop.
    Type: Grant
    Filed: February 9, 2023
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Che Wu, Tsung-Yang Hung, Ming-Yih Wang
  • Publication number: 20240094288
    Abstract: A circuit screening system including a target circuit under test receiving a first testing signal in a first period and a second testing signal in a second period; and a clock generating circuit providing a clock signal to the target circuit under test, the clock signal triggering the target circuit under test to receive the first testing signal in the first period and the second testing signal in the second period; the clock signal having a first profile and a second profile in the first period and the second period, respectively, and the first profile and the second profile having a phase difference.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Inventors: CHI-CHE WU, TSUNG-YANG HUNG, JIA-MING GUO, YI-NA FANG, MING-YIH WANG
  • Publication number: 20240028093
    Abstract: Described are system and methods for maximizing charging power to an information handling system (IHS) from a programmable power supply (PPS). The IHS and the PPS initiate communication with one another. Information is exchanged as to the capabilities of the PPS for providing charging power to battery cells of the IHS, and information as to the battery cells of the HIS. Charging power from the PPS based on the configuration and capability of the battery cells of the IHS, and charging power is kept at a maximum power throughout charging of the battery cells.
    Type: Application
    Filed: July 22, 2022
    Publication date: January 25, 2024
    Applicant: Dell Products L.P.
    Inventors: Geroncio Ong Tan, Wei Cheng Yu, Chi-Che Wu, Tsung-Cheng Liao
  • Publication number: 20240003985
    Abstract: Systems and methods that may be implemented to determine electrical characteristic/s of one or more power supply cable/s that are coupled to supply power from a power supply to a battery-powered information handling system, and to take one or more actions based on the determined electrical characteristic/s. The disclosed systems and methods may be so implemented to detect values of input voltage and input current that are provided from the power supply cable to a battery-powered information handling system, and to take one or more actions based on these detected values of input voltage and input current, such as power supply voltage compensation, protection of the power supply, alerts to the battery-powered information handling system, and/or warnings to a user of the battery-powered information handling system.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Inventors: Merle Wood, III, Chin-Jui Liu, Chi-Che Wu, Tsung-Cheng Liao, Wei-Cheng Yu
  • Patent number: 11852682
    Abstract: A circuit screening system including a target circuit under test receiving a first testing signal in a first period and a second testing signal in a second period; a power circuit providing a supply voltage to the target circuit under test, the supply voltage maintaining at a first voltage level in the first period and deviating from the first voltage level, and maintaining at the first voltage level in the second period; and a clock generating circuit providing a clock signal to the target circuit under test, the clock signal triggering the target circuit under test to receive the first testing signal in the first period and the second testing signal in the second period; the clock signal having a first profile and a second profile in the first period and the second period, respectively, and the first profile and the second profile having a phase difference.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Che Wu, Tsung-Yang Hung, Jia-Ming Guo, Yi-Na Fang, Ming-Yih Wang
  • Patent number: 11799252
    Abstract: A high-performance single barrel power connector for receiving electric power may be capable of receiving more than 330 W up to approximately 600 W of power. The V+ pin and V? pin may each be configured with a large plurality of contact points for connecting to a power plug. A connector body retaining the V+ pin and V? pin may configured with openings to expose more of the V+ pin and V? pin to air and allow the V+ pin and V? pin to extend out of the power connector for convective and conductive heat transfer. A shell having a high thermal conductivity may be connected to the V? pin and V? pin and further connected to a bracket for increased heat transfer away from the V+ and V? pins.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: October 24, 2023
    Inventors: Andrew Thomas Sultenfuss, Tsung-Cheng Liao, Wei-Cheng Yu, Chi-Che Wu
  • Patent number: 11757231
    Abstract: A connector includes a receptacle and a plug. The receptacle includes a first terminal of a first gender. The plug includes a second terminal of a second gender opposite to the first gender. The plug further includes a cover and an insert. The cover plugs into the receptacle. The insert includes the second terminal. The insert inserts into the cover such that the first terminal makes an electrical connection with the second terminal.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: September 12, 2023
    Assignee: Dell Products L.P.
    Inventors: Wei-Cheng Yu, Robert D. Widenhofer, Chi-Che Wu
  • Publication number: 20230273257
    Abstract: An apparatus for testing a device under test (DUT) is provided. The apparatus includes a power supply device and a data generating device. The power supply device is configured to provide a first voltage and a second voltage to the DUT. The data generating device is configured to provide first data to the DUT. The power supply device is configured to provide the first voltage to the DUT in a first time duration. The data generating device is configured to provide the first data to the DUT in the first time duration. The power supply device is configured to provide the second voltage to the DUT in a second time duration after the first time duration. The second voltage is different from the first voltage.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 31, 2023
    Inventors: CHI-CHE WU, TSUNG-YANG HUNG, MING-YIH WANG, JIA-MING GUO
  • Publication number: 20230238750
    Abstract: A high-performance single barrel power connector for receiving electric power may be capable of receiving more than 330 W up to approximately 600 W of power. The V+ pin and V? pin may each be configured with a large plurality of contact points for connecting to a power plug. A connector body retaining the V+ pin and V? pin may configured with openings to expose more of the V+ pin and V? pin to air and allow the V+ pin and V? pin to extend out of the power connector for convective and conductive heat transfer. A shell having a high thermal conductivity may be connected to the V? pin and V? pin and further connected to a bracket for increased heat transfer away from the V+ and V? pins.
    Type: Application
    Filed: January 24, 2022
    Publication date: July 27, 2023
    Inventors: Andrew Thomas Sultenfuss, Tsung-Cheng Liao, Wei-Cheng Yu, Chi-Che Wu
  • Publication number: 20230194598
    Abstract: A method is provided and includes several operations: testing multiple scan chains in multiple shift cycles to obtain multiple values; determining at least one fail chain in the scan chains and determining at least one fail shift cycle corresponding to at least one fail value in the values; mapping the at least one fail chain and the at least one fail shift cycle to the scan chains to identify the at least one fail flip flop; and identifying at least one fault site corresponding to the at least one fail flip flop.
    Type: Application
    Filed: February 9, 2023
    Publication date: June 22, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Che WU, Tsung-Yang HUNG, Ming-Yih WANG