Patents by Inventor Chi Cheah

Chi Cheah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12002747
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include a semiconductor package including a package substrate, a first semiconductor die on the package substrate, a second semiconductor die on the package substrate, a third semiconductor die on the package substrate, and a bridge interconnect at least partially embedded in the package substrate. The bridge interconnect can include a first bridge section coupling the first semiconductor die to the second semiconductor die, a second bridge section coupling the second semiconductor die to the third semiconductor die, and a power-ground section between the first section and the second section, the power-ground section comprising first and second conductive traces coupled to the second semiconductor die.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: June 4, 2024
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jenny Shio Yin Ong, Seok Ling Lim, Kooi Chi Ooi, Jackson Chung Peng Kong
  • Publication number: 20240145365
    Abstract: A device is provided, including a dielectric layer, a plurality of first conductive segments within the dielectric layer and spaced apart from each other by respective first spacings, and a plurality of second conductive segments within the dielectric layer and spaced apart from each other by respective second spacings. The plurality of second conductive segments may be over and spaced apart from the plurality of first conductive segments by the dielectric layer. A respective one of the first conductive segments may at least partially extend across a corresponding one of the second spacings, and a respective one of the second conductive segments may at least partially extend across a corresponding one of the first spacings.
    Type: Application
    Filed: October 28, 2022
    Publication date: May 2, 2024
    Inventors: Bok Eng CHEAH, Seok Ling LIM, Jenny Shio Yin ONG, Kooi Chi OOI, Jackson Chung Peng KONG
  • Publication number: 20240145420
    Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a substrate including a plurality of first contact pads, a plurality of second contact pads, and a plurality of third contact pads. The electronic assembly may include a first device including a first footprint coupled to the substrate at a first surface. The electronic assembly may include a frame arranged between the first device and the substrate, the frame including a dielectric material, the frame further including a main frame extending around the first device, and further including a plurality of sub-frames encircling the plurality of first contact pads and the plurality of second contact pads on the substrate, wherein the frame may further include a conductive layer extending at least partially across the main frame.
    Type: Application
    Filed: October 28, 2022
    Publication date: May 2, 2024
    Inventors: Bok Eng CHEAH, Seok Ling LIM, Kooi Chi OOI, Jackson Chung Peng KONG, Jenny Shio Yin ONG
  • Publication number: 20240136269
    Abstract: A device is provided, including a package substrate including at least one opening extending through the package substrate, and an interconnect structure including a first segment and a second segment. The first segment may extend under a bottom surface of the package substrate and may further extend beyond a footprint of the package substrate. The second segment may extend vertically from the first segment and may extend at least partially through the at least one opening of the package substrate.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Inventors: Bok Eng CHEAH, Seok Ling LIM, Jenny Shio Yin ONG, Jackson Chung Peng KONG, Kooi Chi OOI
  • Publication number: 20240071856
    Abstract: The present disclosure is directed to an electronic assembly and method of forming thereof. The electronic assembly may include a substrate and a first die with first and second opposing surfaces. The first die may be coupled to the substrate at the first surface. At least one first trench may extend partially through the first die from the second surface. A stiffener may be attached to the substrate. The stiffener may have a cavity that accommodates the first die, in which the second surface of the first die faces the stiffener. A thermally conductive layer may be positioned between the stiffener and the first die. The conductive layer at least partially fills the at least one first trench.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Bok Eng CHEAH, Seok Ling LIM, Jenny Shio Yin ONG, Jackson Chung Peng KONG, Kooi Chi OOI
  • Publication number: 20060129328
    Abstract: The present invention provides a method for designing three-dimensional scaffold structures that are anatomically accurate and possess the necessary internal porous micro-architecture design, wherein the porous micro-architecture is necessary for the proliferation and colonization of cultured cells that lead to tissue formation. The design method of the present invention utilizes the patient data derived from medical imaging modalities (e.g., CT or MRI) in combination with computer data manipulation techniques. The present invention further provides that the resultant scaffold design can be easily manufactured by Rapid Prototyping fabrication techniques.
    Type: Application
    Filed: September 30, 2005
    Publication date: June 15, 2006
    Inventors: Chin Leo, Chi Cheah