Patents by Inventor Chi-Cheng Huang

Chi-Cheng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210226029
    Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Inventors: Yu-Lien HUANG, Chi-Wen LIU, Clement Hsingjen WANN, Ming-Huan TSAI, Zhao-Cheng CHEN
  • Patent number: 11062644
    Abstract: A display device includes a display panel, a light source module and a control unit. The display panel includes plural display areas. The light source module includes plural light source units. The light source units are configured to output plural light beams to illuminate the display areas of the display panel. The control unit is coupled to the light source module and configured to receive a frame data. The frame data includes plural subframe data, and the subframe data are displayed on the display areas. The control unit is further configured to control a first light source unit of the light source units to adjust a brightness corresponding to a first color of a first light beam of the light beams according to a ratio of the first color. The ratio of the first color is related to a first subframe data of the subframe data.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: July 13, 2021
    Assignee: E Ink Holdings Inc.
    Inventors: Sheng-Chieh Tai, Yu-Nan Pao, Hsin-Tao Huang, Yi-Pai Huang, Fang-Cheng Lin, Chi-Wen Chang
  • Publication number: 20210134979
    Abstract: A method for fabricating gate structures includes providing a substrate, configured to have a first region and a second region. Dummy gate structures are formed on the substrate at the first and second regions, wherein each of the dummy gate structures has a first gate insulating layer on the substrate and a dummy gate on the first gate insulating layer. An inter-layer dielectric layer is formed over the dummy gate structures. The inter-layer dielectric layer is polished to expose all of the dummy gates. The dummy gates are removed. The first gate insulating layer at the second region is removed. A second gate insulating layer is formed on the substrate at the second region, wherein the first gate insulating layer is thicker than the second insulating layer. Metal gates are formed on the first and the second insulating layer.
    Type: Application
    Filed: October 31, 2019
    Publication date: May 6, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Chih-Hao Pan, Chi-Cheng Huang, Kuo-Lung Li, Szu-Ping Wang, Po-Hsuan Chen, Chao-Sheng Cheng
  • Patent number: 10580780
    Abstract: Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: March 3, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Zi-Jun Liu, Ping-Chia Shih, Chi-Cheng Huang, Kuo-Lung Li, Hung-Wei Lin, An-Hsiu Cheng, Chih-Hao Pan, Cheng-Hua Chou, Chih-Hung Wang
  • Publication number: 20190378846
    Abstract: Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.
    Type: Application
    Filed: June 11, 2018
    Publication date: December 12, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Zi-Jun Liu, Ping-Chia Shih, Chi-Cheng Huang, Kuo-Lung Li, Hung-Wei Lin, An-Hsiu Cheng, Chih-Hao Pan, Cheng-Hua Chou, Chih-Hung Wang
  • Patent number: 10340282
    Abstract: A semiconductor memory device includes a substrate, having a plurality of cell regions, wherein the cell regions are parallel and extending along a first direction. A plurality of STI structures is disposed in the substrate, extending along the first direction to isolate the cell regions, wherein the STI structures have a uniform height lower than the substrate in the cell regions. A selection gate line is extending along a second direction and crossing over the cell regions and the STI structures. A control gate line is adjacent to the selection gate line in parallel extending along the second direction and also crosses over the cell regions and the STI structures. The selection gate line and the control gate line together form a two-transistor (2T) memory cell.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: July 2, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Shu-Hung Yu, Chun-Hung Cheng, Chuan-Fu Wang, An-Hsiu Cheng, Ping-Chia Shih, Chi-Cheng Huang, Kuo-Lung Li, Chia-Hui Huang, Chih-Yao Wang, Zi-Jun Liu, Chih-Hao Pan
  • Patent number: 10312250
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of isolation structures, a charge storage layer, and a conductive layer. The substrate has a memory region and a logic region. The substrate in the memory region has a plurality of semiconductor fins. The isolation structures are disposed in the substrate to isolate the semiconductor fins. The semiconductor fins are protruded beyond the isolation structures. The charge storage layer covers the semiconductor fins. The conductive layer is disposed across the semiconductor fins and the isolation structures such that the charge storage layer is disposed between the conductive layer and the semiconductor fins.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: June 4, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Hsuan-Chun Tseng, Hsueh-Chun Hsiao, Tzu-Yun Chang, Chi-Cheng Huang, Ping-Chia Shih
  • Publication number: 20180182900
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate having a tunneling well, a tunneling oxide layer, a charge storage layer and a control gate. The tunneling oxide layer is disposed on the tunneling well. The tunneling oxide layer includes a first tunneling oxide segment having a first thickness, a second tunneling oxide segment having a second thickness, and a third tunneling oxide segment having a third thickness, and the first thickness, the second thickness and the third thickness are different from each other. The charge storage layer is disposed on the tunneling oxide layer, and the control gate is disposed on the charge storage layer.
    Type: Application
    Filed: February 21, 2017
    Publication date: June 28, 2018
    Inventors: Ya-Sheng Feng, Chi-Cheng Huang, Ping-Chia Shih, Hung-Wei Lin, Yu-Chun Chen, Ling-Hsiu Chou, An-Hsiu Cheng
  • Patent number: 10008615
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate having a tunneling well, a tunneling oxide layer, a charge storage layer and a control gate. The tunneling oxide layer is disposed on the tunneling well. The tunneling oxide layer includes a first tunneling oxide segment having a first thickness, a second tunneling oxide segment having a second thickness, and a third tunneling oxide segment having a third thickness, and the first thickness, the second thickness and the third thickness are different from each other. The charge storage layer is disposed on the tunneling oxide layer, and the control gate is disposed on the charge storage layer.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: June 26, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Sheng Feng, Chi-Cheng Huang, Ping-Chia Shih, Hung-Wei Lin, Yu-Chun Chen, Ling-Hsiu Chou, An-Hsiu Cheng
  • Publication number: 20170200729
    Abstract: An integrated circuit process includes the following steps. A substrate including a flash cell area and a logic area is provided. A first sacrificial gate on the substrate of the flash cell area and a second sacrificial gate on the substrate of the logic area are formed, and a dielectric layer covers the substrate beside the first sacrificial gate and the second sacrificial gate. The first sacrificial gate is removed to forma first recess in the dielectric layer. An oxide/nitride/oxide layer is formed to conformally cover surfaces of the first recess. An integrated circuit formed by said integrated circuit process is also provided.
    Type: Application
    Filed: January 12, 2016
    Publication date: July 13, 2017
    Inventors: Tseng-Fang Dai, Ping-Chia Shih, Chi-Cheng Huang, Kun-I Chou, Hung-Wei Lin, Ching-Wen Yang
  • Patent number: 9412851
    Abstract: A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: August 9, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Chun Chang, Ping-Chia Shih, Chi-Cheng Huang, Kuo-Lung Li, Kun-I Chou, Chung-Che Huang, Chia-Cheng Hsu, Mu-Jia Liu
  • Patent number: 9397202
    Abstract: A method for fabricating semiconductor device is disclosed. Preferably, two hard masks are utilized to define the width of the first gate (may serve for a control gate) and the width of the second gate (may serve for a select gate). The widths are thus well controlled. For example, in an embodiment, the width of the select gate may be adjusted in advance as desired, and the select gate is protected by the second hard mask during an etch process, so as to obtain a select gate which upper portion has an appropriate width. Accordingly the semiconductor device would still have an excellent performance upon miniaturization.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: July 19, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiang-Chen Lee, Ping-Chia Shih, Chi-Cheng Huang, Wan-Fang Chung, Yu-Chun Chang, Je-Yi Su
  • Publication number: 20160204230
    Abstract: A method for fabricating semiconductor device is disclosed. Preferably, two hard masks are utilized to define the width of the first gate (may serve for a control gate) and the width of the second gate (may serve for a select gate). The widths are thus well controlled. For example, in an embodiment, the width of the select gate may be adjusted in advance as desired, and the select gate is protected by the second hard mask during an etch process, so as to obtain a select gate which upper portion has an appropriate width. Accordingly the semiconductor device would still have an excellent performance upon miniaturization.
    Type: Application
    Filed: March 23, 2016
    Publication date: July 14, 2016
    Inventors: Hsiang-Chen Lee, Ping-Chia Shih, Chi-Cheng Huang, Wan-Fang Chung, Yu-Chun Chang, Je-Yi Su
  • Patent number: 9331183
    Abstract: A semiconductor device including a first gate structure and a second gate structure immediately adjacent to each other with a spacer therebetween. Line width of the top of the second gate structure is not less than that of the bottom thereof. A fabrication method thereof is also disclosed. A transient first gate structure and a temporary gate structure are formed by etching through a first hard mask. A second gate structure is formed between a first spacer and a second spacer opposite to each other and disposed respectively on the transient first gate structure and temporary gate structure. The second gate structure is covered with a second hard mask. An etch process is performed through a patterned photoresist layer to remove exposed first hard mask and temporary gate structure and to partially remove exposed portion of first hard mask and transient first gate structure to form the first gate structure.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: May 3, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiang-Chen Lee, Ping-Chia Shih, Chi-Cheng Huang, Wan-Fang Chung, Yu-Chun Chang, Je-Yi Su
  • Patent number: 9202701
    Abstract: A method for manufacturing a silicon-oxide-nitride-oxide-silicon non-volatile memory cell includes following steps. An implant region is formed in a substrate. A first oxide layer, a nitride layer, and a second oxide layer are formed and stacked on the substrate. A density of the second oxide layer is higher than a density of the first oxide layer. A first photoresist pattern is formed on the second oxide layer and corresponding to the implant region. A first wet etching process is then performed to form an oxide hard mask. A second wet etching process is performed to remove the nitride layer exposed by the oxide hard mask to form a nitride pattern. A cleaning process is then performed to remove the oxide hard mask and the first oxide layer exposed by the nitride pattern, and a gate oxide layer is then formed on the nitride pattern.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: December 1, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-I Chou, Chi-Cheng Huang, Yu-Chun Chang, Ling-Hsiu Chou, Tseng-Fang Dai, Jheng-Jie Huang, Ping-Chia Shih
  • Publication number: 20150179748
    Abstract: A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.
    Type: Application
    Filed: December 23, 2013
    Publication date: June 25, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Chun Chang, Ping-Chia Shih, Chi-Cheng Huang, Kuo-Lung Li, Kun-I Chou, Chung-Che Huang, Chia-Cheng Hsu, Mu-Jia Liu
  • Patent number: 8921185
    Abstract: A method for fabricating an integrated circuit includes the following steps of: providing a substrate with at least one isolation structure formed therein so as to separate the substrate into a first active region with a first stacked structure formed thereon and a second active region with a second stacked structure formed thereon; forming an interlayer dielectric layer covering the first stacked structure and the second stacked structure; and planarizing the interlayer dielectric layer to expose the top surface of the first stacked structure, wherein the second stacked structure is still covered by the interlayer dielectric layer after planarizing.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: December 30, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Hsiang-Chen Lee, Ping-Chia Shih, Ke-Chi Chen, Chih-Ming Wang, Chi-Cheng Huang
  • Publication number: 20140353739
    Abstract: A semiconductor device including a first gate structure and a second gate structure immediately adjacent to each other with a spacer therebetween. Line width of the top of the second gate structure is not less than that of the bottom thereof. A fabrication method thereof is also disclosed. A transient first gate structure and a temporary gate structure are formed by etching through a first hard mask. A second gate structure is formed between a first spacer and a second spacer opposite to each other and disposed respectively on the transient first gate structure and temporary gate structure. The second gate structure is covered with a second hard mask. An etch process is performed through a patterned photoresist layer to remove exposed first hard mask and temporary gate structure and to partially remove exposed portion of first hard mask and transient first gate structure to form the first gate structure.
    Type: Application
    Filed: June 3, 2013
    Publication date: December 4, 2014
    Inventors: Hsiang-Chen Lee, Ping-Chia Shih, Chi-Cheng Huang, Wan-Fang Chung, Yu-Chun Chang, Je-Yi Su
  • Publication number: 20140227844
    Abstract: A method for fabricating an integrated circuit includes the following steps of: providing a substrate with at least one isolation structure formed therein so as to separate the substrate into a first active region with a first stacked structure formed thereon and a second active region with a second stacked structure formed thereon; forming an interlayer dielectric layer covering the first stacked structure and the second stacked structure; and planarizing the interlayer dielectric layer to expose the top surface of the first stacked structure, wherein the second stacked structure is still covered by the interlayer dielectric layer after planarizing.
    Type: Application
    Filed: April 17, 2014
    Publication date: August 14, 2014
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Hsiang-Chen LEE, Ping-Chia Shih, Ke-Chi Chen, Chih-Ming Wang, Chi-Cheng Huang
  • Publication number: 20140091383
    Abstract: A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.
    Type: Application
    Filed: December 5, 2013
    Publication date: April 3, 2014
    Applicant: United Microelectronics Corp.
    Inventors: Ko-Chi Chen, Ping-Chia Shih, Chih-Ming Wang, Chi-Cheng Huang, Hsiang-Chen Lee