Abstract: A micro light-emitting diode display device includes a substrate, a first planarization layer, a first light-emitting element, and a second planarization layer. The first planarization layer is disposed on the substrate and has a first opening. The first opening has a first opening inner wall. The first light-emitting element is disposed on the substrate, in the first opening, and separated from the first opening inner wall. The second planarization layer is disposed on the substrate and between the first planarization layer and the first light-emitting element. The second planarization layer is in contact with the first light-emitting element.

Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.

Abstract: A method for manufacturing a golf ball having a multi-layered pattern is provided. Firstly, a semi-finished product of the golf ball is provided and includes a ball-shaped body and a base layer covering an outer surface of the ball-shaped body. Then, the semi-finished product of the golf ball is rotated at a predetermined rotation speed, and a color paint is applied to the semi-finished product of the golf ball by spraying from each of an upper position, a middle position, and a lower position. The multi-layered pattern includes an upper-layer pattern area, a mid-layer pattern area, and a lower-layer pattern area that are different in color from each other.

Abstract: A semiconductor structure including a substrate, a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer and in physical contact with the first dielectric layer, an opening on the substrate and having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, an conductive layer disposed on the second dielectric layer at two sides of the opening and in physical contact with the second dielectric layer, a contact structure disposed in the lower portion of the opening, and a passivation layer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the conductive layer.

Abstract: Provided are a tank support jig and a tank cleaning method. The tank support jig for supporting a cylindrical tank includes a curved body having a first end and a second end that face with an interval in between; and a connecting member disposed across the interval, the connecting member connecting the first end and the second end of the curved body such that the interval is adjustable, in which the curved body and the connecting member form an annular structure for the tank that is to be placed horizontally inside the annular structure with the curved body in close contact with at least part of an outer circumferential face of the tank along a circumferential direction of the tank.

Abstract: A system and methods of forming a dielectric material within a trench are described herein. In an embodiment of the method, the method includes introducing a first precursor into a trench of a dielectric layer, such that portions of the first precursor react with the dielectric layer and attach on sidewalls of the trench. The method further includes partially etching portions of the first precursor on the sidewalls of the trench to expose upper portions of the sidewalls of the trench. The method further includes introducing a second precursor into the trench, such that portions of the second precursor react with the remaining portions of the first precursor to form the dielectric material at the bottom of the trench.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Abstract: A process for converting a portion of a dielectric fill material into a hard mask includes a nitrogen treatment or nitrogen plasma to convert a portion of the dielectric fill material into a nitrogen-like layer for serving as a hard mask to form an edge area of a device die by an etching process. After forming the edge area, another dielectric fill material is provided in the edge area. In the completed device, a gate cut area can have a gradient of nitrogen concentration at an upper portion of the gate cut dielectric of the gate cut area.

Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.

Abstract: A vacuum processing apparatus (110) for deposition of a material on a substrate is provided. The vacuum processing apparatus (110) includes a vacuum chamber comprising a processing area (111); a deposition apparatus (112) within the processing area (111) of the vacuum chamber; a cooling surface (113) inside the vacuum chamber; and one or more movable shields (220) between the cooling surface (113) and the processing area (111).

Abstract: The present invention provides an audio control circuit comprising an USB interface and a processing circuit is disclosed. The USB interface is used to connect to a host device, and the processing circuit is configured to perform enumeration with the host device via the USB interface, and the processing circuit is further configured to determine if the host device operates in a BIOS stage or an operating system stage to generate a control signal according to packets of the enumeration. When the processing circuit determines that the host device operates in the BIOS stage, the processing circuit generates the control signal to enable a de-pop circuit; and when the processing circuit determines that the host device operates in the operating system stage, the processing circuit generates the control signal to disable the de-pop circuit.

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

Abstract: A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure.

Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.

Abstract: A serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof are provided. A SPI architecture includes a master IC and a slave IC. When the SPI IC is a master IC, the SPI IC generates first command information for a slave IC, generates first debugging information corresponding to the first command information, and sends the first command information and the first debugging information to the slave IC through a SPI channel. When the SPI IC is the slave IC, the SPI IC receives second command information and second debugging information sent by the master IC through the SPI channel and checks the second command information by using the second debugging information. When the SPI IC is a target slave circuit selected by the master IC, the SPI IC executes the second command information under a condition that the second command information is checked and is correct.

Abstract: The disclosure provides a daisy-chain serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof. The daisy-chain SPI IC includes a first MISO interface circuit, a second MISO interface circuit, a first data enable (DE) interface circuit, and a second DE interface circuit. When the daisy-chain SPI IC is a target slave circuit selected by a master IC for reading target data, the first DE interface circuit outputs a DE signal to the master IC, and the first MISO interface circuit sends back the target data to the master IC based on the timing of the DE signal. When the daisy-chain SPI IC is not the target slave circuit, the signal received by the second DE interface circuit is transmitted to the first DE interface circuit, and the data received by the second MISO interface circuit is transmitted to the first MISO interface circuit.

Abstract: A heat-dissipating device includes a casing and a heat dissipating fin set. The casing has a first hole structure. The heat dissipating fin set includes a protruding fin, a sheltering component and a bridging component. A hollow chamber of the protruding fin has a first opening and a second opening adjacent to each other. The first opening is connected to an inner space of the casing. The sheltering component is disposed on the protruding fin to shelter the second opening. The bridging component is connected to the protruding fin and fixed onto the first hole structure.

Abstract: The invention provides a large touch display integrated (LTDI) circuit and an operation method thereof. The LTDI circuit is suitable as a slave IC of an serial peripheral interface (SPI) architecture. The LTDI circuit includes an open-drain circuit and a reload circuit. An output terminal of the open-drain circuit is configured to be coupled to a correctness wire outside the LTDI circuit. The correctness wire is also coupled to an input terminal of a master IC of the SPI architecture, and a potential of the correctness wire is pulled up by a pull-up resistor. The reload circuit is coupled to an input terminal of the open-drain circuit. The reload circuit is configured to check a correctness of a boot up code from the master IC to generate a correctness check result. The reload circuit returns the correctness check result to the master IC via the open-drain circuit and the correctness wire.

Abstract: The invention provides a large touch display integrated (LTDI) circuit and an operation method thereof. The LTDI circuit is suitable as a slave IC of an serial peripheral interface (SPI) architecture. The LTDI circuit includes an open-drain circuit and a reload circuit. An output terminal of the open-drain circuit is configured to be coupled to a correctness wire outside the LTDI circuit. The correctness wire is also coupled to an input terminal of a master IC of the SPI architecture, and a potential of the correctness wire is pulled up by a pull-up resistor. The reload circuit is coupled to an input terminal of the open-drain circuit. The reload circuit is configured to check a correctness of a boot up code from the master IC to generate a correctness check result. The reload circuit returns the correctness check result to the master IC via the open-drain circuit and the correctness wire.

Abstract: The disclosure provides a daisy-chain serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof. The daisy-chain SPI IC includes a first MISO interface circuit, a second MISO interface circuit, a first data enable (DE) interface circuit, and a second DE interface circuit. When the daisy-chain SPI IC is a target slave circuit selected by a master IC for reading target data, the first DE interface circuit outputs a DE signal to the master IC, and the first MISO interface circuit sends back the target data to the master IC based on the timing of the DE signal. When the daisy-chain SPI IC is not the target slave circuit, the signal received by the second DE interface circuit is transmitted to the first DE interface circuit, and the data received by the second MISO interface circuit is transmitted to the first MISO interface circuit.