Patents by Inventor Chi-Cherng Jeng

Chi-Cherng Jeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having dual channels, complementary semiconductor device and manufacturing method thereof
    Patent number: 9768073
    Abstract: Provided is a semiconductor device having dual channels including a first portion and a second portion sharing a buried gate pillar. The buried gate pillar extends from a first surface of a substrate toward a second surface opposite to the first surface. The first portion includes the buried gate pillar, a first gate dielectric layer at a first sidewall of the buried gate pillar and a first doped region set aside the first gate dielectric layer. A first channel is provided in the substrate between the first gate dielectric layer and the first doped region set. The second portion includes the buried gate pillar, a second gate dielectric layer at a second sidewall of the buried gate pillar and a second doped region set aside the second gate dielectric layer. A second channel is provided in the substrate between the second gate dielectric layer and the second doped region set.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Chung Lin, Chen-Chieh Chiang, Chi-Cherng Jeng
  • Structure of dielectric grid for a semiconductor device
    Patent number: 9768214
    Abstract: A device includes a substrate having a non-pixel region and a pixel region; sensor elements disposed in the pixel region; and a metal layer disposed over the substrate. The metal layer includes a metal shield disposed in the non-pixel region and first trenches over the respective sensor elements in the pixel region. The device further includes a dielectric layer disposed over the metal layer. The dielectric layer has second trenches over the respective sensor elements and third trenches over the metal shield. The first trenches are completely through the metal layer, and the second trenches are partially through the dielectric layer.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: September 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chun-Hao Chou, Yin-Chieh Huang, Kuo-Cheng Lee, Chi-Cherng Jeng, Hsin-Chi Chen
  • FIN FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME
    Publication number: 20170250268
    Abstract: A FinFET includes a semiconductor substrate, a plurality of insulators, a gate stack, and a strained material. The semiconductor substrate includes at least one semiconductor fin thereon. The semiconductor fin includes source/drain regions and a channel region, and a width of the source/drain regions is larger than a width of the channel region. The insulators are disposed on the semiconductor substrate and the semiconductor fin is sandwiched by the insulators. The gate stack is located over the channel region of the semiconductor fin and over portions of the insulators. The strained material covers the source/drain regions of the semiconductor fin. In addition, a method for fabricating the FinFET is provided.
    Type: Application
    Filed: February 25, 2016
    Publication date: August 31, 2017
    Inventors: Ru-Shang Hsiao, Chii-Ming Wu, Chi-Cherng Jeng
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
    Publication number: 20170250089
    Abstract: Semiconductor devices and manufacturing method of the same are disclosed. A semiconductor device includes a substrate, a p-type MOS transistor, an n-type MOS transistor and a cured flowable oxide layer. The substrate includes a first region and a second region. The p-type MOS transistor is in the first region. The n-type MOS transistor is in the second region. The cured flowable oxide layer covers the p-type MOS transistor and the n-type MOS transistor, wherein a first strain of the cured flowable oxide layer applying to the p-type MOS transistor is different from a second strain of the cured flowable oxide layer applying to the n-type MOS transistor, and the difference therebetween is greater than 0.002 Gpa.
    Type: Application
    Filed: February 26, 2016
    Publication date: August 31, 2017
    Inventors: Ting-Huang Kuo, Chia-Pin Lo, Wei-Barn Chen, Chen-Chieh Chiang, Chii-Ming Wu, Chi-Cherng Jeng
  • SEMICONDUCTOR DEVICE HAVING DUAL CHANNELS, COMPLEMENTARY SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170250116
    Abstract: Provided is a semiconductor device having dual channels including a first portion and a second portion sharing a buried gate pillar. The buried gate pillar extends from a first surface of a substrate toward a second surface opposite to the first surface. The first portion includes the buried gate pillar, a first gate dielectric layer at a first sidewall of the buried gate pillar and a first doped region set aside the first gate dielectric layer. A first channel is provided in the substrate between the first gate dielectric layer and the first doped region set. The second portion includes the buried gate pillar, a second gate dielectric layer at a second sidewall of the buried gate pillar and a second doped region set aside the second gate dielectric layer. A second channel is provided in the substrate between the second gate dielectric layer and the second doped region set.
    Type: Application
    Filed: February 26, 2016
    Publication date: August 31, 2017
    Inventors: Yi-Chung Lin, Chen-Chieh Chiang, Chi-Cherng Jeng
  • SUPPORT STRUCTURE FOR INTEGRATED CIRCUITRY
    Publication number: 20170243908
    Abstract: Among other things, one or more support structures for integrated circuitry and techniques for forming such support structures are provided. A support structure comprises one or more trench structures, such as a first trench structure and a second trench structure formed around a periphery of integrated circuitry. In some embodiments, one or more trench structures are formed according to partial substrate etching, such that respective trench structures are formed into a region of a substrate. In some embodiments, one or more trench structures are formed according to discontinued substrate etching, such that respective trench structures comprise one or more trench portions separated by separation regions of the substrate. The support structure mitigates stress energy from reaching the integrated circuitry, and facilitates process-induced charge release from the integrated circuitry.
    Type: Application
    Filed: May 1, 2017
    Publication date: August 24, 2017
    Inventors: Volume CHIEN, Yun-Wei CHENG, I-I CHENG, Shiu-Ko JANGJIAN, Chi-Cherng JENG, Chih-Mu HUANG
  • FIN FIELD EFFECT TRANSISTOR AND FABRICATING METHOD THEREOF
    Publication number: 20170229580
    Abstract: A FinFET including a substrate, a plurality of insulators and a gate stack is provided. The substrate includes a plurality of trenches and at least one semiconductor fin between the trenches. The insulators are disposed in the trenches. The semiconductor fin includes a first portion embedded between the insulators; a necking portion disposed on the first portion, the necking portion being uncovered by the insulators; and a second portion disposed on the necking portion, wherein a width of the necking portion is less than a width of the first portion. The gate stack partially covers the semiconductor fin, the at least one recess and the insulators.
    Type: Application
    Filed: February 5, 2016
    Publication date: August 10, 2017
    Inventors: Wen-Sheng Lin, Chen-Chieh Chiang, Chi-Cherng Jeng
  • Integrated circuit and manufacturing method thereof
    Patent number: 9721883
    Abstract: Integrated circuits and manufacturing methods of the same are disclosed. The integrated circuit includes a transistor, a first dielectric layer, an etch stop layer, a first via and a first conductive layer. The first dielectric layer is disposed between the transistor and the etch stop layer. The first via is disposed in the first dielectric layer and the etch stop layer, and electrically connected to the transistor. The first conductive layer is in contact with the first via, wherein the first via is disposed between the first conductive layer and the transistor, and the etch stop layer is aside a portion of the first via adjacent to the first conductive layer.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: August 1, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Lung Lai, Chen-Chieh Chiang, Chi-Cherng Jeng, Shiu-Ko JangJian
  • Light sensing device with outgassing hole in a light shielding layer and an anti-reflection film
    Patent number: 9722099
    Abstract: A light sensing device includes a substrate, a light sensing area on the substrate, and a light shielding layer over the substrate. The light shielding layer does not cover the light sensing area. At least one outgassing hole is formed through the light shielding layer.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: August 1, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Han Tsai, Kuo-Cheng Lee, Shiu-Ko JangJian, Chi-Cherng Jeng
  • METHOD OF FABRICATING TANTALUM NITRIDE BARRIER LAYER AND SEMICONDUCTOR DEVICE THEREOF
    Publication number: 20170207316
    Abstract: A method of fabricating tantalum nitride barrier layer in an ultra low threshold voltage semiconductor device is provided. The method includes forming a high-k dielectric layer over a semiconductor substrate. Subsequently, a tantalum nitride barrier layer is formed on the high-k dielectric layer. The tantalum nitride barrier layer has a Ta:N ratio between 1.2 and 3. Next, a plurality of first metal gates is formed on the tantalum nitride barrier layer. The first metal gates are patterned, and then a second metal gate is formed on the tantalum nitride barrier layer.
    Type: Application
    Filed: March 18, 2016
    Publication date: July 20, 2017
    Inventors: Chi-Cheng HUNG, Yu-Sheng WANG, Weng-Cheng CHEN, Hao-Han WEI, Ming-Ching CHUNG, Chi-Cherng JENG
  • Bonding pad structure with dense via array
    Patent number: 9711468
    Abstract: A bonding pad structure comprises a first dielectric layer, a first conductive island in a second dielectric layer over the first dielectric layer and a via array having a plurality of vias in a third dielectric layer over the first conductive island. The structure also comprises a plurality of second conductive islands in a fourth dielectric layer over the via array. The second conductive islands are each separated from one another by a dielectric material of the fourth dielectric layer and in contact with at least one via of the via array. The structure further comprises a substrate over the second conductive islands. The substrate has an opening defined therein that exposes at least one second conductive island. The structure additionally comprises a bonding pad over the substrate. The bonding pad is in contact with the at least one second conductive island through the opening in the substrate.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: July 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Han Tsai, Jung-Chi Jeng, Yueh-Ching Chang, Volume Chien, Huang-Ta Huang, Chi-Cherng Jeng
  • Capacitor structure of integrated circuit chip and method of fabricating the same
    Patent number: 9698214
    Abstract: In accordance with some embodiments of the present disclosure, a capacitor structure of an integrated circuit chip includes an insulation layer, a first electrode, and a second electrode. The insulation layer includes an insulation partition and has a first trench and a second trench separated from the first trench by the insulation partition. The first electrode is disposed in the first trench. The second electrode is disposed in the second trench. The first electrode first electrode is arranged along a spiral trajectory and surrounds a spiral channel. The second electrode is disposed within the spiral channel.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nan-Chi Lu, Chen-Chieh Chiang, Chi-Cherng Jeng
  • Manufacturing method of forming a semiconductor wafer structure
    Patent number: 9666555
    Abstract: A method of manufacturing a semiconductor structure includes providing a first wafer including a surface, removing some portions of the first wafer over the surface to form a plurality of recesses extended over at least a portion of the surface of the first wafer, providing a second wafer, and disposing the second wafer over the surface of the first wafer.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: May 30, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Chun Chen, Chiu-Jung Chen, Fu-Tsun Tsai, Shiu-Ko Jangjian, Chi-Cherng Jeng, Hsin-Chi Chen
  • Metal pad offset for multi-layer metal layout
    Patent number: 9659859
    Abstract: A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: I-Chih Chen, Ying-Hao Chen, Chi-Cherng Jeng, Volume Chien, Fu-Tsun Tsai, Kun-Huei Lin
  • FINFET GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20170125298
    Abstract: A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure is fluorine incorporated and includes a n-type work function metal layer overlying the first high-k dielectric layer. The n-type work function metal layer includes a TiAl (titanium aluminum) alloy, in which an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3. The semiconductor device further includes a p-type gate structure over a second semiconductor fin, in which the p-type gate structure is fluorine incorporated includes a p-type work function metal layer overlying the second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), in which an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1.
    Type: Application
    Filed: December 16, 2016
    Publication date: May 4, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko JANGJIAN, Ren-Hau YU, Chi-Cherng JENG
  • Support structure for integrated circuitry
    Patent number: 9640456
    Abstract: Among other things, one or more support structures for integrated circuitry and techniques for forming such support structures are provided. A support structure comprises one or more trench structures, such as a first trench structure and a second trench structure formed around a periphery of integrated circuitry. In some embodiments, one or more trench structures are formed according to partial substrate etching, such that respective trench structures are formed into a region of a substrate. In some embodiments, one or more trench structures are formed according to discontinued substrate etching, such that respective trench structures comprise one or more trench portions separated by separation regions of the substrate. The support structure mitigates stress energy from reaching the integrated circuitry, and facilitates process-induced charge release from the integrated circuitry.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: May 2, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Volume Chien, Yun-Wei Cheng, I-I Cheng, Shiu-Ko JangJian, Chi-Cherng Jeng, Chih-Mu Huang
  • Image sensor device and method for forming the same
    Patent number: 9627426
    Abstract: Embodiments of the disclosure provide an image sensor device. The image sensor device includes a semiconductor substrate. The semiconductor substrate has a front surface, a back surface opposite to the front surface, a light-sensing region close to the front surface, and a trench adjacent to the light-sensing region. The image sensor device includes a reflective layer positioned on an inner wall of the trench, wherein the reflective layer has a light reflectivity ranging from about 70% to about 100%.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: April 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Volume Chien, Yu-Heng Cheng, Fu-Tsun Tsai, Hsi-Jung Wu, Chi-Cherng Jeng
  • MECHANISMS FOR FORMING IMAGE SENSOR DEVICE
    Publication number: 20170098675
    Abstract: A method for forming an image sensor device is provided. The method includes forming a photodetector in a semiconductor substrate and forming a shielding layer over the semiconductor substrate. The method also includes forming a dielectric layer over the shielding layer and partially removing the dielectric layer to form a recess. The method further includes partially removing the shielding layer through the recess. In addition, the method includes forming a filter in the recess after the shielding layer is partially removed.
    Type: Application
    Filed: December 15, 2016
    Publication date: April 6, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Volume CHIEN, Yun-Wei CHENG, Shiu-Ko JANGJIAN, Zhe-Ju LIU, Kuo-Cheng LEE, Chi-Cherng JENG
  • Image sensor and method for manufacturing thereof
    Patent number: 9608021
    Abstract: An image sensor is provided including a substrate, an array of photosensitive units, a grid, a light-tight layer and a plurality of color filters. In the image sensor, the grid has a top surface, and the light-tight layer is disposed on the top surface of the grid. Due to the light-tight layer on the grid, an incident light entering into the grid can be blocked by the light-tight layer, so that the crosstalk effect is reduced significantly. Further, a method for manufacturing the image sensor also provides herein.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: March 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Wei Cheng, Zhe-Ju Liu, Kuo-Cheng Lee, Chi-Cherng Jeng, Chun-Hao Chou, Yin-Chieh Huang, Wan-Chen Huang
  • STRUCTURE AND FORMATION METHOD OF FIN-LIKE FIELD EFFECT TRANSISTOR
    Publication number: 20170076994
    Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure.
    Type: Application
    Filed: November 7, 2016
    Publication date: March 16, 2017
    Inventors: Shiu-Ko JANGJIAN, Tzu-Kai LIN, Chi-Cherng JENG