Patents by Inventor Chi-Chiang Lin

Chi-Chiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High voltage tolerant I/O circuit using native NMOS transistor for improved performance
    Patent number: 7113018
    Abstract: An I/O circuit between a low voltage circuit and a high voltage circuit includes a switching device, a native device and a gate control logic circuit. The switching device provides an output signal to the high voltage circuit in response to a data input signal received from the low voltage circuit. The native device passes the data input signal to control an on or off state of the switching device. The gate control logic circuit operates in an output disabled mode and an output enabled mode. In the output disabled mode, the gate control logic circuit disables the native device for preventing a leakage current passing therethrough. In the output enabled mode, the gate control logic circuit enables the native device to pass the data input signal through without a substantial voltage drop, thereby enhancing a switching speed of the switching device.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: September 26, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Tsai Li, Chi-Chiang Lin
  • High voltage tolerant I/O circuit using native NMOS transistor for improved performance
    Publication number: 20060091917
    Abstract: An I/O circuit between a low voltage circuit and a high voltage circuit includes a switching device, a native device and a gate control logic circuit. The switching device provides an output signal to the high voltage circuit in response to a data input signal received from the low voltage circuit. The native device passes the data input signal to control an on or off state of the switching device. The gate control logic circuit operates in an output disabled mode and an output enabled mode. In the output disabled mode, the gate control logic circuit disables the native device for preventing a leakage current passing therethrough. In the output enabled mode, the gate control logic circuit enables the native device to pass the data input signal through without a substantial voltage drop, thereby enhancing a switching speed of the switching device.
    Type: Application
    Filed: October 28, 2004
    Publication date: May 4, 2006
    Inventors: Kuo-Tsai Li, Chi-Chiang Lin