Abstract: A programmable non-overlap clock generator is disclosed. This clock generator includes a primary clock signal input terminal for providing a primary clock signal, and a selection signal input terminal for providing at least one selection signal. The present invention also includes a first logic gate, whose first input terminal is coupled to receive an inverted signal of the primary clock signal. Further, the first input terminal of a second logic gate is coupled to receive the primary clock signal. A first programmable delay means, connected between an output of the first logic gate and the second input terminal of the second logic gate, is used to delay an output signal from the first logic gate a predetermined amount of time according to the selection signal.

Abstract: A structure and method for forming multiplication of a b-bit multiplicand X and a b-bit multiplier Y to generate a product P is disclosed. The present invention includes cells C.sub.mn configured in a b.times.b array, and pieces of means for generating partial product X.sub.mn, wherein outputs of the partial product generating means are connected to first inputs of the cells respectively. The second inputs of the cells C.sub.mn, where m=0, 1, 2, . . . , b-2, and n=1, 2, . . . , b-1, are connected to first outputs of the cells C.sub.m+1, n-1 respectively, and the second inputs of the cells C.sub.b-1, n, where n=1, 2, . . . , b-1, are connected to second outputs of the cells C.sub.n-1, b-1 respectively. Further, the third inputs of the cells C.sub.mn, where m=0, 1, 2, . . . , b-1, and n=2, 3, . . . , b-1, are connected to the second outputs of the cells C.sub.m, n-1. Therefore, a portion of the product P.sub.f, where f=0, 1, . . . , b-1, comes from the first outputs of the cells C.sub.

Abstract: A self-setup non-overlap clock generator is disclosed. This clock generator includes a primary clock signal input terminal for providing a primary clock signal, and a selection signal input terminal for providing at least one selection signal. The present invention also includes a first logic gate having a first input terminal coupled to receive an inverted signal of the primary clock signal. Further, a second logic gate is provided, having a first input terminal coupled to receive the primary clock signal. A first programmable delay portion is used to delay an output signal from the first logic gate an amount of time according to the selection signal, and a second programmable delay portion is used to delay an output signal from the second logic gate a predetermined amount of time according to the selection signal. Therefore, a first clock signal is generated from the output of the first logic gate, and a second clock signal is generated from the output of the second logic gate.