Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.

Abstract: A pressure sensing unit is provided. The pressure sensing unit includes a membrane and a pressure sensing pad group. The membrane has a first surface and a second surface. The pressure sensing pad group includes a first pressure sensing pad, a second pressure sensing pad, and a ground pad that are spaced apart from one another. The ground pad and one among the first pressure sensing pad and the second pressure sensing pad are located at the first surface of the membrane, another one among the first pressure sensing pad and the second pressure sensing pad is located at the second surface of the membrane, and an orthographic projection of the ground pad projected onto a reference plane is located between orthographic projections of the first pressure sensing pad and the second pressure sensing pad that are projected onto the reference plane. Therefore, a signal-to-noise ratio can be increased and an erroneous detection can be prevented.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: The present invention relates to a method of fabricating polysilicon film by Nickel and Copper induced lateral crystallization for the TFT-LCD, comprising the step of: a) a thin (˜4 nm) Copper and Nickel being evaporated onto the substrate; b) a amorphous-silicon film (˜50 nm) being evaporated onto thereof obtained according to a); c) applying annealing at less than 600° C. to thereof obtained according to b) for fast fabricating poly-silicon film. It is approximately 10 times faster than that of Ni induced polysilicon. The present invention is to provide a low-temperature (<600° C.) fast growth rate process to convert the hydrogenated amorphous silicon (a-Si:H) films to polysilicon film for substantially time-saving process and industrial applicability.