Patents by Inventor Chi-Chin Yeh

Chi-Chin Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Retardation layer for preventing diffusion of metal layer and fabrication method thereof
    Patent number: 6156655
    Abstract: A retardation layer of a copper damascene process and the fabrication method thereof, to replace the conventional barrier layer with a laminated layer. The laminated layer combines the conventional barrier layer with a porous layer, wherein the porous layer can be formed either above or below the barrier layer to improve the retardation of the copper atom diffusion. Preferably, the porous layer is formed above the barrier layer.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: December 5, 2000
    Assignees: United Microelectronics Corp., United Semiconductor Corp.
    Inventors: Ming-Ching Huang, Chih-Rong Chen, Kuai-Jung Ho, Wen-Yuan Huang, Chi-Chin Yeh
  • Method of fabricating embedded gate electrodes
    Patent number: 6066532
    Abstract: A method of fabricating an embedded gate electrode is disclosed.
    Type: Grant
    Filed: October 18, 1999
    Date of Patent: May 23, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Rong Chen, Chi-Chin Yeh