Patents by Inventor Chi-Ching Ho

Chi-Ching Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12672553
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a full-panel wafer is provided and includes a plurality of electronic bodies arranged in an array at intervals, a plurality of trenches are formed across the electronic bodies along a first direction on the full-panel wafer, so that the trenches on a single electronic body are arranged parallel to each other at interval and along a second direction perpendicular to the first direction. Then, in a singulation process, any trench can be selected for cutting to obtain a plurality of electronic elements of a required size. Finally, each of the electronic elements is disposed on a packaging region of a carrier structure, so that each of the electronic elements is electrically connected to at least a portion of electrical contact pads in the packaging region.
    Type: Grant
    Filed: July 14, 2023
    Date of Patent: June 30, 2026
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Che-Yu Lee, Chi-Ching Ho, Chao-Chiang Pu, Yi-Min Fu, Po-Yuan Su
  • Publication number: 20260173888
    Abstract: An electronic package is provided, in which a first electronic element and a second electronic element stacked on each other are embedded in a cladding layer, a circuit structure electrically connected to the second electronic element is formed on the cladding layer, and a passive element and a package module are disposed on the circuit structure, so as to shorten the transmission distance of electrical signals between the package module and the second electronic element.
    Type: Application
    Filed: February 6, 2026
    Publication date: June 18, 2026
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min FU, Hung-Kai WANG, Chi-Ching HO, Yih-Jenn JIANG, Yu-Po WANG
  • Publication number: 20260173841
    Abstract: An electronic package is provided and includes a carrying structure, a wiring structure, an electronic structure, an encapsulation layer and a connecting element. The wiring structure is disposed on the carrying structure. The electronic structure is disposed on the wiring structure and includes a plurality of first conductive bumps and a plurality of second conductive bumps. The plurality of first conductive bumps are electrically connected to the wiring structure. The encapsulation layer is formed on the wiring structure and covers the electronic structure. The plurality of second conductive bumps are exposed from the encapsulation layer. The connecting element is disposed on the encapsulation layer and is electrically connected to the plurality of second conductive bumps. An electronic device having the electronic package and a manufacturing method of the electronic package are further provided.
    Type: Application
    Filed: May 7, 2025
    Publication date: June 18, 2026
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min FU, Chi-Ching HO, Yu-Po WANG
  • Publication number: 20260083000
    Abstract: An electronic package and a manufacturing method thereof are provided. The electronic package includes a carrier structure, an electronic element, a bridge element, an encapsulation layer, and a photonic element. The electronic element and the bridge element are disposed on a second surface of the carrier structure to be electrically connected to the carrier structure. The encapsulation layer covers the electronic element and the bridge element. The photonic element is disposed on a surface of the encapsulation layer and is electrically connected to the bridge element. In the electronic package and the manufacturing method thereof, the photonic element is disposed after the formation and grinding of the encapsulation layer are completed, the photonic element can be prevented from covering by the encapsulation, thereby contamination or damage to the light transmitters and the light receivers of the photonic element can be avoided.
    Type: Application
    Filed: January 13, 2025
    Publication date: March 19, 2026
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min FU, Chi-Ching HO, Yu-Po WANG
  • Patent number: 12575420
    Abstract: An electronic package is provided, in which a first electronic element and a second electronic element stacked on each other are embedded in a cladding layer, a circuit structure electrically connected to the second electronic element is formed on the cladding layer, and a passive element and a package module are disposed on the circuit structure, so as to shorten the transmission distance of electrical signals between the package module and the second electronic element.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: March 10, 2026
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min Fu, Hung-Kai Wang, Chi-Ching Ho, Yih-Jenn Jiang, Yu-Po Wang
  • Publication number: 20260047498
    Abstract: An electronic package is provided, in which a circuit structure is stacked on a carrier structure having a routing layer via support structures, where electronic elements are disposed on upper and lower sides of the circuit structure and the carrier structure, and the electronic elements and the support structures are encapsulated by a cladding layer, such that the electronic package can effectively increase the packaging density to meet the requirements of multi-functional end products.
    Type: Application
    Filed: October 15, 2025
    Publication date: February 12, 2026
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chi-Ching HO
  • Patent number: 12525505
    Abstract: An electronic package is provided, where a laterally diffused metal oxide semiconductor (LDMOS) type electronic structure is mounted onto a complementary metal oxide semiconductor (CMOS) type electronic element to be integrated into a chip module, thereby shortening electrical transmission path between the electronic structure and the electronic element so as to reduce the communication time between the electronic structure and the electronic element.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: January 13, 2026
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min Fu, Chi-Ching Ho, Yu-Po Wang
  • Publication number: 20260011645
    Abstract: An electronic package is provided, in which an electronic module and at least one support member are disposed on a substrate structure having a circuit layer, such that the stress on the substrate structure is dispersed through the at least one support member to eliminate the problem of stress concentration and prevent the substrate structure from warping.
    Type: Application
    Filed: September 11, 2025
    Publication date: January 8, 2026
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min FU, Chi-Ching HO, Chao-Chiang PU, Yu-Po WANG
  • Publication number: 20260011698
    Abstract: An electronic structure, an electronic package and a manufacturing method thereof are provided, in which a carrier and an adhesive layer are used to support or fix the electronic structure and the electronic package, and double carriers are used to support or fix the electronic structure and the electronic package, thereby avoiding the warpage problem of the electronic structure and the electronic package.
    Type: Application
    Filed: October 18, 2024
    Publication date: January 8, 2026
    Inventors: Jui-Cheng LIN, Chi-Ching HO, Chao-Chiang PU, Yi-Min FU, Chiu-Ling CHEN
  • Patent number: 12476229
    Abstract: An electronic package is provided, in which a circuit structure is stacked on a carrier structure having a routing layer via support structures, where electronic elements are disposed on upper and lower sides of the circuit structure and the carrier structure, and the electronic elements and the support structures are encapsulated by a cladding layer, such that the electronic package can effectively increase the packaging density to meet the requirements of multi-functional end products.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: November 18, 2025
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Wen-Jung Tsai, Chi-Ching Ho
  • Publication number: 20250336739
    Abstract: An electronic package and a manufacturing method thereof are provided. The electronic package at least includes an electronic element, a conductive pillar, a reinforcement member, an encapsulation layer and a redistribution layer. The conductive pillar and the reinforcement member are both disposed around the electronic element. The electronic element, the conductive pillar and the reinforcement member are encapsulating by the encapsulation layer. The redistribution layer is disposed on the same side of the electronic element, the conductive pillar, the reinforcement member and the encapsulation layer, and electrically connected to the electronic element and the conductive pillar. The reinforcement member has high hardness and a tunable coefficient of thermal expansion (CTE), which can enhance the strength and rigidity of the electronic package to reduce the warpage of the electronic package.
    Type: Application
    Filed: August 1, 2024
    Publication date: October 30, 2025
    Inventors: Chao-Chiang PU, Chi-Ching HO, Yi-Min FU, Yu-Po WANG, Che-Yu LEE
  • Patent number: 12438094
    Abstract: An electronic package is provided, in which an electronic module and at least one support member are disposed on a substrate structure having a circuit layer, such that the stress on the substrate structure is dispersed through the at least one support member to eliminate the problem of stress concentration and prevent the substrate structure from warping.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: October 7, 2025
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min Fu, Chi-Ching Ho, Chao-Chiang Pu, Yu-Po Wang
  • Publication number: 20250311452
    Abstract: The present disclosure provides an electronic package having an electronic module, an optoelectronic component disposed on and electrically connected to the electronic module, and a lens module disposed on a side of the optoelectronic component. By the implementation of the present disclosure, the electronic package can be used with a laser without the need to provide a shelf for supporting and fixing an optical fiber. Therefore, the structure and manufacturing process of the electronic package can be effectively simplified, thereby improving the yield and the speed of manufacturing and reducing the manufacturing costs.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 2, 2025
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Che-Yu LEE, Chi-Ching HO, Chao-Chiang PU, Yi-Min FU, Jui-Cheng LIN
  • Patent number: 12412819
    Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.
    Type: Grant
    Filed: April 23, 2024
    Date of Patent: September 9, 2025
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min Fu, Chi-Ching Ho, Cheng-Yu Kang, Yu-Po Wang
  • Patent number: 12412820
    Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.
    Type: Grant
    Filed: April 24, 2024
    Date of Patent: September 9, 2025
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min Fu, Chi-Ching Ho, Cheng-Yu Kang, Yu-Po Wang
  • Publication number: 20250279375
    Abstract: An electronic package is provided and includes an electronic structure and a plurality of conductive pillars embedded in a cladding layer, a circuit structure formed on the cladding layer, and a reinforcing member bonded to a side surface of the cladding layer, where a plurality of electronic elements are disposed on and electrically connected to the circuit structure, such that the electronic structure electrically bridges any two of the electronic elements via the circuit structure, so as to enhance the structural strength of the electronic package and avoid warpage by means of the design of the reinforcing member.
    Type: Application
    Filed: May 19, 2025
    Publication date: September 4, 2025
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Chiang PU, Chi-Ching HO, Yi-Min FU, Yu-Po WANG, Fang-Lin TSAI
  • Patent number: 12334452
    Abstract: An electronic package is provided and includes an electronic structure and a plurality of conductive pillars embedded in a cladding layer, a circuit structure formed on the cladding layer, and a reinforcing member bonded to a side surface of the cladding layer, where a plurality of electronic elements are disposed on and electrically connected to the circuit structure, such that the electronic structure electrically bridges any two of the electronic elements via the circuit structure, so as to enhance the structural strength of the electronic package and avoid warpage by means of the design of the reinforcing member.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: June 17, 2025
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Fang-Lin Tsai
  • Publication number: 20250183239
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a passive element and an interposer structure are disposed on a carrier structure, the passive element is encapsulated by an encapsulation layer, and the electronic element is disposed on and electrically connected to the passive element and the interposer structure. Therefore, by the design of the electronic element electrically connecting to the passive element, the power transmission path is shortened and the resistance is reduced, thereby achieving the effect of reducing power loss.
    Type: Application
    Filed: June 5, 2024
    Publication date: June 5, 2025
    Inventors: Yi-Min FU, Chi-Ching HO, Yu-Po WANG
  • Publication number: 20250140770
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a photonic integrated circuit chip and an electronic integrated circuit chip are disposed on opposite sides of an interposer respectively, and the photonic integrated circuit chip and the electronic integrated circuit chip can accomplish signal connection with each other via a plurality of conductive vias in the interposer directly, thereby reducing the power consumption and transmission delay of the signals transmitted between the circuits.
    Type: Application
    Filed: March 27, 2024
    Publication date: May 1, 2025
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Che-Yu LEE, Chi-Ching HO, Chao-Chiang PU, Yi-Min FU, Po-Yuan SU
  • Publication number: 20250140765
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a plurality of photonic integrated circuit chips and an auxiliary electronic element are separately configured on a package module to shorten the transmission distance of the optical signal. Therefore, the signal transmission rate of a circuit structure can be increased, thereby improving the overall operating performance of the electronic package.
    Type: Application
    Filed: April 10, 2024
    Publication date: May 1, 2025
    Inventors: Yi-Min FU, Chi-Ching HO, Chao-Chiang PU, Yu-Po WANG