Patents by Inventor Chi-Ching Ho

Chi-Ching Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250087601
    Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Inventors: Chao-Chiang PU, Chi-Ching HO, Yi-Min FU, Yu-Po WANG, Po-Yuan SU
  • Publication number: 20250079254
    Abstract: An electronic package is provided and includes: a thermally conductive chip; a circuit structure having a circuit layer; and an electronic component disposed between the circuit structure and the thermally conductive chip and electrically connected to the circuit layer, so as to dissipate the heat generated during the operation of the electronic component via the thermally conductive chip. A method of manufacturing the electronic package is further provided.
    Type: Application
    Filed: January 4, 2024
    Publication date: March 6, 2025
    Inventors: Po-Yuan SU, Chi-Ching HO, Chao-Chiang PU, Yi-Min FU, Che-Yu LEE
  • Publication number: 20250038113
    Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.
    Type: Application
    Filed: October 16, 2024
    Publication date: January 30, 2025
    Inventors: Chao-Chiang PU, Chi-Ching HO, Yi-Min FU, Yu-Po WANG, Shuai-Lin LIU
  • Patent number: 12199047
    Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: January 14, 2025
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Po-Yuan Su
  • Publication number: 20250015054
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Application
    Filed: September 18, 2024
    Publication date: January 9, 2025
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching HO, Bo-Hao MA, Yu-Ting XUE, Ching-Hung TSENG, Guan-Hua LU, Hong-Da CHANG
  • Patent number: 12176291
    Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: December 24, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Shuai-Lin Liu
  • Publication number: 20240371721
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a heat sink with an opening is disposed on an electronic component of a carrier structure, a heat dissipation material is formed in the opening, and a heat dissipation lid is disposed on the opening to cover the heat dissipation material, such that the problem of insufficient heat dissipation due to the loss of the heat dissipation material can be prevented from occurring to the electronic component.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 7, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min FU, Chi-Ching HO, Chao-Chiang PU, Yu-Po WANG
  • Publication number: 20240363545
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a full-panel wafer is provided and includes a plurality of electronic bodies arranged in an array at intervals, a plurality of trenches are formed across the electronic bodies along a first direction on the full-panel wafer, so that the trenches on a single electronic body are arranged parallel to each other at interval and along a second direction perpendicular to the first direction. Then, in a singulation process, any trench can be selected for cutting to obtain a plurality of electronic elements of a required size. Finally, each of the electronic elements is disposed on a packaging region of a carrier structure, so that each of the electronic elements is electrically connected to at least a portion of electrical contact pads in the packaging region.
    Type: Application
    Filed: July 14, 2023
    Publication date: October 31, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Che-Yu LEE, Chi-Ching HO, Chao-Chiang PU, Yi-Min FU, Po-Yuan SU
  • Patent number: 12125828
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Grant
    Filed: September 11, 2023
    Date of Patent: October 22, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching Ho, Bo-Hao Ma, Yu-Ting Xue, Ching-Hung Tseng, Guan-Hua Lu, Hong-Da Chang
  • Publication number: 20240290701
    Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 29, 2024
    Inventors: Yi-Min FU, Chi-Ching HO, Cheng-Yu KANG, Yu-Po WANG
  • Publication number: 20240274519
    Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.
    Type: Application
    Filed: April 23, 2024
    Publication date: August 15, 2024
    Inventors: Yi-Min FU, Chi-Ching HO, Cheng-Yu KANG, Yu-Po WANG
  • Publication number: 20240264389
    Abstract: An electronic package and the manufacturing method thereof are provided, in which a photonic element and an electronic element are embedded in an encapsulation layer, and the photonic element has an external contact area exposed from the encapsulation layer, such that signals of the electronic element can be directly transmitted to an optical fiber via the external contact area of the photonic element to achieve the purpose of photoelectric integration.
    Type: Application
    Filed: May 2, 2023
    Publication date: August 8, 2024
    Inventors: Chao-Chiang PU, Chi-Ching HO, Yi-Min FU, Che-Yu LEE, Po-Yuan SU
  • Patent number: 12051641
    Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: July 30, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min Fu, Chi-Ching Ho, Cheng-Yu Kang, Yu-Po Wang
  • Publication number: 20240153884
    Abstract: An electronic package is provided, in which a first electronic element and a second electronic element stacked on each other are embedded in a cladding layer, a circuit structure electrically connected to the second electronic element is formed on the cladding layer, and a passive element and a package module are disposed on the circuit structure, so as to shorten the transmission distance of electrical signals between the package module and the second electronic element.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 9, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min FU, Hung-Kai WANG, Chi-Ching HO, Yih-Jenn JIANG, Yu-Po WANG
  • Publication number: 20240128249
    Abstract: An electronic package is provided, in which a circuit structure is stacked on a carrier structure having a routing layer via support structures, where electronic elements are disposed on upper and lower sides of the circuit structure and the carrier structure, and the electronic elements and the support structures are encapsulated by a cladding layer, such that the electronic package can effectively increase the packaging density to meet the requirements of multi-functional end products.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 18, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chi-Ching HO
  • Patent number: 11923337
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: March 5, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching Ho, Bo-Hao Ma, Yu-Ting Xue, Ching-Hung Tseng, Guan-Hua Lu, Hong-Da Chang
  • Publication number: 20240038685
    Abstract: An electronic package is provided and includes an electronic structure and a plurality of conductive pillars embedded in a cladding layer, a circuit structure formed on the cladding layer, and a reinforcing member bonded to a side surface of the cladding layer, where a plurality of electronic elements are disposed on and electrically connected to the circuit structure, such that the electronic structure electrically bridges any two of the electronic elements via the circuit structure, so as to enhance the structural strength of the electronic package and avoid warpage by means of the design of the reinforcing member.
    Type: Application
    Filed: September 22, 2022
    Publication date: February 1, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Fang-Lin Tsai
  • Publication number: 20230420420
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Application
    Filed: September 11, 2023
    Publication date: December 28, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Ching HO, Bo-Hao MA, Yu-Ting XUE, Ching-Hung TSENG, Guan-Hua LU, Hong-Da CHANG
  • Publication number: 20230282586
    Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.
    Type: Application
    Filed: May 10, 2022
    Publication date: September 7, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Shuai-Lin Liu
  • Publication number: 20230253331
    Abstract: An electronic package is provided, in which an electronic module and at least one support member are disposed on a substrate structure having a circuit layer, such that the stress on the substrate structure is dispersed through the at least one support member to eliminate the problem of stress concentration and prevent the substrate structure from warping.
    Type: Application
    Filed: August 29, 2022
    Publication date: August 10, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min Fu, Chi-Ching Ho, Chao-Chiang Pu, Yu-Po Wang