Patents by Inventor Chi-Ching Pu

Chi-Ching Pu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230102875
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor structure is formed on a first surface of a silicon substrate. The semiconductor structure has a first surface facing the silicon substrate. At least one outer circuit is bonded to the semiconductor structure. A molding compound layer is formed covering a second surface of the silicon substrate. A part of the molding compound layer is removed for exposing the silicon substrate. The silicon substrate is removed for exposing the first surface of the semiconductor structure.
    Type: Application
    Filed: October 13, 2021
    Publication date: March 30, 2023
    Applicant: GLC SEMI CONDUCTOR GROUP (SH) CO., LTD.
    Inventors: Chi-Ching Pu, Shun-Min Yeh
  • Publication number: 20230053074
    Abstract: A semiconductor device includes at least one active region, a first dielectric layer, a gate structure, and an air void. The active region includes a III-V compound semiconductor layer. The first dielectric layer is disposed on the active region. The gate structure is disposed on the active region, and at least a part of the gate structure is disposed in the first dielectric layer. The air void is disposed in the first dielectric layer, and at least a part of the air void is disposed at two opposite sides of the gate structure in a horizontal direction.
    Type: Application
    Filed: August 12, 2021
    Publication date: February 16, 2023
    Applicant: GLC SEMI CONDUCTOR GROUP (SH) CO., LTD.
    Inventors: Che-Jui Chang, Chi-Ching Pu, Shun-Min Yeh
  • Publication number: 20220286125
    Abstract: A power switch circuit includes an internal node; a first field-effect transistor including a first drain, a first gate and a first source; a second field-effect transistor including a second drain, a second gate and a second source, wherein the first drain is coupled to a voltage supply terminal, the first gate is coupled to the second source, the first source and the second drain are coupled to the internal node, and the second source is coupled to a ground; and a regulating circuit is coupled to the internal node, wherein the regulating circuit is configured to regulate a voltage value of the internal node after the power switch circuit is activated.
    Type: Application
    Filed: December 7, 2021
    Publication date: September 8, 2022
    Applicant: GLC SEMI CONDUCTOR GROUP (SH) CO., LTD.
    Inventors: Kuo-Chang Kao, Chi-Ching Pu, Shun-Min Yeh
  • Patent number: 11411099
    Abstract: A semiconductor device includes a substrate, a first III-V compound layer, a gate electrode, drain trenches, and at least one drain electrode. The drain trenches are disposed and arranged with high integrity. The substrate has a first side and a second side opposite to the first side. The first III-V compound layer is disposed at the first side of the substrate. The gate electrode is disposed on the first III-V compound layer. Each of the drain trenches extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The drain trenches are arranged regularly. The drain electrode is disposed in at least one of the drain trenches.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: August 9, 2022
    Assignee: GLC SEMICONDUCTOR GROUP (CQ) CO., LTD.
    Inventors: Chi-Ching Pu, Shun-Min Yeh
  • Publication number: 20200381554
    Abstract: A semiconductor device includes a substrate, a first III-V compound layer, a gate electrode, drain trenches, and at least one drain electrode. The drain trenches are disposed and arranged with high integrity. The substrate has a first side and a second side opposite to the first side. The first III-V compound layer is disposed at the first side of the substrate. The gate electrode is disposed on the first III-V compound layer. Each of the drain trenches extends from the second side of the substrate toward the first side of the substrate and penetrates the substrate. The drain trenches are arranged regularly. The drain electrode is disposed in at least one of the drain trenches.
    Type: Application
    Filed: July 23, 2019
    Publication date: December 3, 2020
    Inventors: Chi-Ching Pu, Shun-Min Yeh