Abstract: A battery charging apparatus includes a battery compartment having a receptacle that is configured to receive a battery pack. The battery charging apparatus includes a first heat exchange module and/or a second heat exchange module. The first heat exchange module includes a plenum surrounding the receptacle, where the plenum includes a chamber to receive a fluid. The plenum also includes a plurality of flow guides disposed in the chamber to define a variable flow passage for the fluid. The second heat exchange module includes a battery connector and a heat sink thermally coupled to the battery connector. The heat sink is arranged to dissipate thermal energy from the battery pack.

Abstract: A processor capable of changing redundant processing node comprises a plurality of processing nodes and a plurality of comparators. The plurality of processing nodes comprises a first processing node, a second processing node, and a third processing node, wherein the first processing node performs a first computation, the second processing node selectively performs the first computation or a second computation, and the third processing node performs the second computation. The plurality of comparators comprises a first comparator and a second comparator, wherein the first comparator connects to the first and second processing nodes to compare whether the results of the first computation performed by the first and second processing nodes are identical, and the second comparator connects to the second and third processing nodes to compare whether results of the second computation performed by the second and third processing nodes are identical.

Abstract: A processor capable of changing redundant processing node comprises a plurality of processing nodes and a plurality of comparators. The plurality of processing nodes comprises a first processing node, a second processing node, and a third processing node, wherein the first processing node performs a first computation, the second processing node selectively performs the first computation or a second computation, and the third processing node performs the second computation. The plurality of comparators comprises a first comparator and a second comparator, wherein the first comparator connects to the first and second processing nodes to compare whether the results of the first computation performed by the first and second processing nodes are identical, and the second comparator connects to the second and third processing nodes to compare whether results of the second computation performed by the second and third processing nodes are identical.

Abstract: A testing method for a chip with an embedded non-volatile memory and the chip is provided. A remapping circuit and the non-volatile memory are connected to a processor. The non-volatile memory has a test area and an area under test. The test area stores a test program, and the area under test stores data under test. When the processor tests the chip, the processor outputs an original instruction address, and the remapping circuit remaps the original instruction address to generate a remapped instruction address. The processor reads the test program in the test area, and executes the test program to read the data under test in the area under test and to perform a test of toggling the logic circuit.

Abstract: A testing method for a chip with an embedded non-volatile memory and the chip is provided. A remapping circuit and the non-volatile memory are connected to a processor. The non-volatile memory has a test area and an area under test. The test area stores a test program, and the area under test stores data under test. When the processor tests the chip, the processor outputs an original instruction address, and the remapping circuit remaps the original instruction address to generate a remapped instruction address. The processor reads the test program in the test area, and executes the test program to read the data under test in the area under test and to perform a test of toggling the logic circuit.

Abstract: A system communicating processors is provided. The system comprises a first processor, a second processor, a SRAM and a DMA unit. The DMA unit further comprises a detection unit to determine whether the SRAM is accessed by the second processor, wherein when the SRAM is not accessed by the second processor, the access control of the SRAM is transferred to the DMA unit, and data communication between the first processor and the second processor is transmitted by the DMA unit.

Abstract: A storage device includes a firmware memory, a buffer memory, a processor and a memory update controller. When the storage device is under a normal mode, the memory update controller is in an idle state. The processor controls the storage device to fetch an update firmware and store the update firmware into the buffer memory. When the storage device is under a firmware update mode, the processor is in an idle state. The memory update controller fetches the update firmware from the buffer memory and stores the update firmware into the firmware memory without the processor executing an update routine code.

Abstract: An optical disc drive includes a firmware memory, a buffer memory, and a system control chip. The system control chip includes a processor and a memory update controller. When the optical disc drive is under a normal mode, the memory update controller is in an idle state. The processor controls the optical disc drive to fetch an update firmware from an optical disc and store the update firmware into the buffer memory. When the optical disc drive is under a firmware update mode, the processor is in an idle state. The memory update controller fetches the update firmware from the buffer memory and stores the update firmware into the firmware memory without the processor executing an update routine code.

Abstract: An integrity check method applied to an electronic device includes: fetching at least one portion of external data into a specific memory, where the external data is stored within the electronic device; during fetching the portion of the external data into the specific memory, checking whether the size of the fetched data in the specific memory reaches a predetermined value, where the predetermined value is less than the total size of the external data; and when the size of the fetched data in the specific memory reaches the predetermined value, enabling an integrity check of the fetched data.

Abstract: A method for securing firmware in a memory is provided. Memory data in the memory is checked. If the memory data in the memory meets a criterion, a host is allowed to read and write the entire memory. If not, the host is prevented from reading the entire memory.

Abstract: A data transmitting end utilizes a clock signal to transmit at least a data signal to a data receiving end. An adjustable delay compensation circuit for compensating data transmission delay between the data transmitting end and the data receiving end includes an adjustable delay circuit, a clock gating circuit, and at least a target signal generating circuit. The adjustable delay circuit is used for delaying the clock signal by a programmable delay amount to generate a target delay signal. The clock gating circuit is used for allowing the clock signal to reach the adjustable delay circuit when receiving a data transmission enabling signal. The target signal generating circuit is used for receiving the data signal and for sampling the data signal according to the target delay signal.

Abstract: The present invention discloses an optical disc drive capable of updating firmware, and firmware update method thereof. The disclosed optical disc drive includes a firmware memory, a buffer memory, and a system control chip. The system control chip includes a processor and a memory update controller. When the optical disc drive is under a normal mode, the memory update controller is in an idle state. The processor controls the optical disc drive to fetch an update firmware from an optical disc and store the update firmware into the buffer memory. When the optical disc drive is under a firmware update mode, the processor is in an idle state. The memory update controller fetches the update firmware from the buffer memory and stores the update firmware into the firmware memory without the processor executing an update routine code.