Patents by Inventor Chi-chun Liu

Chi-chun Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12322601
    Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: June 3, 2025
    Assignee: Adeia Semiconductor Solutions LLC
    Inventors: Sean D. Burns, Nelson M. Felix, Chi-Chun Liu, Yann A. M. Mignot, Stuart A. Sieg
  • Publication number: 20240419401
    Abstract: Various embodiments are provided herein for performing a mathematical calculation in a computing environment. A quantization scheme is implemented, allowing at most one (1) non-zero-valued bit in the mantissa of a floating point number.
    Type: Application
    Filed: June 15, 2023
    Publication date: December 19, 2024
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derrick LIU, Ankur AGRAWAL, Chi-Chun LIU, Shyam RAMJI, Naigang WANG
  • Patent number: 12148617
    Abstract: A method of semiconductor manufacture comprising forming a plurality of first mandrels as the top layer of the multi-layered hard mask and forming a first spacer around each of the plurality of first mandrels. Removing the plurality of first mandrels and cutting the first spacer to form a plurality of second mandrels. Forming a second spacer around each of the plurality of second mandrels and forming a first self-aligned pattern that includes a plurality of third mandrels. Removing the plurality of second mandrels and the second spacer and etching the multi-layered hard mask to transfer the first-self aligned pattern to a lower layer of the multi-layered hard mask. Forming a second self-aligned pattern, wherein the second self-aligned pattern is intermixed with the first self-aligned pattern and etching the first self-aligned pattern and the second self-aligned pattern into the conductive metal layer.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: November 19, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chanro Park, Chi-Chun Liu, Stuart Sieg, Yann Mignot, Koichi Motoyama, Hsueh-Chung Chen
  • Patent number: 12113013
    Abstract: A device includes: a first dielectric material; a first metal line in the first dielectric material; a second dielectric material disposed on the first dielectric material and the first metal line; a second metal line in the second dielectric material; and a plurality of metal vias disposed on a same level and connecting the first metal line and the second metal line, wherein the plurality of metal vias comprise a first top via and a bottom via having different sidewall profile angles.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: October 8, 2024
    Assignee: International Business Machines Corporation
    Inventors: Hsueh-Chung Chen, Yann Mignot, Su Chen Fan, Mary Claire Silvestre, Chi-Chun Liu, Junli Wang
  • Patent number: 12046680
    Abstract: A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of spacers disposed on lateral sides of the plurality of gate structures. The respective ones of the plurality of spacers comprise a profile having a first portion comprising a first shape and a second portion comprising a second shape, wherein the first shape is different from the second shape.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: July 23, 2024
    Assignee: International Business Machines Corporation
    Inventors: Yi Song, Chi-Chun Liu, Robin Hsin Kuo Chao, Muthumanickam Sankarapandian
  • Publication number: 20240176584
    Abstract: An apparatus comprising: a first plurality of inputs representing an activation input vector; a second plurality of inputs representing a weight input vector; an analog multiplier-and-accumulator to generate a first analog voltage representing a first multiply-and-accumulate result for the said first inputs and the second inputs; a voltage multiplier that takes the said first analog voltage and produces a second analog voltage representing, a second multiply-and-accumulate result by multiplying at least one scaling factor to the first analog voltage; an analog to digital converter configured to convert the said second analog voltage multiply-and-accumulate result into a digital signal using a limited-precision operation during a neural network inference operation; and a hardware controller configured to determine the at least one scaling factor based on the first multiply-and-accumulate result, or a software controller configured to determine the at least one scaling factor based on the first multiply-and-acc
    Type: Application
    Filed: November 29, 2022
    Publication date: May 30, 2024
    Inventors: Chia-Yu Chen, Andrea Fasoli, Ankur Agrawal, Kyu-hyoun Kim, Chi-Chun LIU, Mauricio J. Serrano, Monodeep Kar, Naigang Wang, Leland Chang
  • Publication number: 20240030036
    Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.
    Type: Application
    Filed: February 14, 2023
    Publication date: January 25, 2024
    Inventors: Sean D. Burns, Nelson M. Felix, Chi-Chun Liu, Yann A.M. Mignot, Stuart A. Sieg
  • Patent number: 11688636
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a plurality of metal lines on substrate, forming a sacrificial dielectric material layer between the metal lines, forming a hardmask over at least one of the metal lines, etching at least one of the metal lines that is not covered by the hardmask, treating the sacrificial dielectric material layer to soften the layer. The method also includes removing the treated sacrificial dielectric material layer.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: June 27, 2023
    Assignee: International Business Machines Corporation
    Inventors: Somnath Ghosh, Karen Elizabeth Petrillo, Cody J. Murray, Ekmini Anuja De Silva, Chi-Chun Liu, Dominik Metzler, John Christopher Arnold
  • Patent number: 11682558
    Abstract: A semiconductor structure includes a set of mandrel lines and a set of non-mandrel lines disposed on a hardmask in an alternating pattern. Spacers are disposed between adjacent mandrel lines and non-mandrel lines. The spacers include a composition which exhibits an etch rate greater than an etch rate of the mandrel lines and the non-mandrel lines.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: June 20, 2023
    Assignee: International Business Machines Corporation
    Inventors: Chi-Chun Liu, Ashim Dutta, Nelson Felix, Ekmini Anuja De Silva
  • Publication number: 20230187350
    Abstract: A semiconductor device includes a conductive line disposed within a dielectric layer, a metal layer disposed over and in direct contact with the conductive line, and a metallization layer disposed over the metal layer such that a protruding segment of the metal layer acts as an interface between the conductive line and the metallization layer. The conductive line is copper (Cu) and the metal layer is ruthenium (Ru). The Ru metal layer includes an upper metal layer section and a lower metal layer section.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 15, 2023
    Inventors: Hsueh-Chung Chen, Yann Mignot, Chi-Chun Liu, Mary Claire Silvestre, Jennifer Oakley
  • Patent number: 11670580
    Abstract: Structures are provided that include a metal-insulator-metal capacitor (MIMCAP) present in the back-end-of-the-line (BEOL). The MIMCAP includes at least one of the bottom electrode and the top electrode having a via portion and a base portion that is formed utilizing a subtractive via etch process. Less via over etching occurs resulting in improved critical dimension control of the bottom and/or top electrodes that are formed by the subtractive via etch process. No bottom liner is present in the MIMCAP thus improving the resistance/capacitance of the device. Also, and in some embodiments, a reduced foot-print area is possible to bring the via portion of the bottom electrode closer to the top electrode.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: June 6, 2023
    Assignee: International Business Machines Corporation
    Inventors: Yann Mignot, Hsueh-Chung Chen, Junli Wang, Mary Claire Silvestre, Chi-Chun Liu
  • Publication number: 20230170293
    Abstract: The present invention relates to integrated circuits and related method steps for forming an IC chip. The method steps result in semiconductor device structures that include redundant same via level formation using a top via subtractive etch and bottom via from dual damascene etch techniques. In embodiments, the same level redundancy via option is optional. Provision of redundant same via level connections using dual damascene processes improves device resistance and capacitive performance. Further method steps result in semiconductor device structures that include a direct super via connection bypassing subtractive etch metal level via formations. These highlighted method steps increase design flexibility—and reduce device footprint (by skipping a metal level) with the benefit of reduced via connection height and shorter metal connections.
    Type: Application
    Filed: November 29, 2021
    Publication date: June 1, 2023
    Inventors: Yann Mignot, Chanro Park, Jacques Simon, Hsueh-Chung Chen, Chi-Chun Liu
  • Publication number: 20230138978
    Abstract: A method of semiconductor manufacture comprising forming a plurality of first mandrels as the top layer of the multi-layered hard mask and forming a first spacer around each of the plurality of first mandrels. Removing the plurality of first mandrels and cutting the first spacer to form a plurality of second mandrels. Forming a second spacer around each of the plurality of second mandrels and forming a first self-aligned pattern that includes a plurality of third mandrels. Removing the plurality of second mandrels and the second spacer and etching the multi-layered hard mask to transfer the first-self aligned pattern to a lower layer of the multi-layered hard mask. Forming a second self-aligned pattern, wherein the second self-aligned pattern is intermixed with the first self-aligned pattern and etching the first self-aligned pattern and the second self-aligned pattern into the conductive metal layer.
    Type: Application
    Filed: November 1, 2021
    Publication date: May 4, 2023
    Inventors: CHANRO PARK, Chi-Chun LIU, Stuart Sieg, Yann Mignot, Koichi Motoyama, Hsueh-Chung Chen
  • Publication number: 20230114163
    Abstract: A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of spacers disposed on lateral sides of the plurality gate structures. The respective ones of the plurality of spacers comprise a profile having a first portion comprising a first shape and a second portion comprising a second shape, wherein the first shape is different from the second shape.
    Type: Application
    Filed: September 27, 2021
    Publication date: April 13, 2023
    Inventors: Yi Song, Chi-Chun Liu, Robin Hsin Kuo Chao, Muthumanickam Sankarapandian
  • Publication number: 20230100368
    Abstract: A device includes: a first dielectric material; a first metal line in the first dielectric material; a second dielectric material disposed on the first dielectric material and the first metal line; a second metal line in the second dielectric material; and a plurality of metal vias disposed on a same level and connecting the first metal line and the second metal line, wherein the plurality of metal vias comprise a first top via and a bottom via having different sidewall profile angles.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Hsueh-Chung Chen, Yann Mignot, Su Chen Fan, Mary Claire Silvestre, Chi-Chun LIU, Junli Wang
  • Publication number: 20230096938
    Abstract: A semiconductor structure includes a set of mandrel lines and a set of non-mandrel lines disposed on a hardmask in an alternating pattern. Spacers are disposed between adjacent mandrel lines and non-mandrel lines. The spacers include a composition which exhibits an etch rate greater than an etch rate of the mandrel lines and the non-mandrel lines.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 30, 2023
    Inventors: Chi-Chun Liu, Ashim Dutta, Nelson Felix, Ekmini Anuja De Silva
  • Patent number: 11610780
    Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: March 21, 2023
    Assignee: TESSERA LLC
    Inventors: Sean D. Burns, Nelson M. Felix, Chi-Chun Liu, Yann A. M. Mignot, Stuart A. Sieg
  • Patent number: 11600325
    Abstract: A resistance switching RAM logic device is presented. The device includes a pair of resistance switching RAM cells that may be independently programed into at least a low resistance state (LRS) or a high resistance state (HRS). The resistance switching RAM logic device may further include a shared output node electrically connected to the pair of resistance switching RAM cells. A logical output may be determined from the programmed resistance state of each of the resistance switching RAM cells.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: March 7, 2023
    Assignee: International Business Machines Corporation
    Inventors: Hsueh-Chung Chen, Mary Claire Silvestre, Soon-Cheon Seo, Chi-Chun Liu, Fee Li Lie, Chih-Chao Yang, Yann Mignot, Theodorus E. Standaert
  • Publication number: 20230063908
    Abstract: Structures are provided that include a metal-insulator-metal capacitor (MIMCAP) present in the back-end-of-the-line (BEOL). The MIMCAP includes at least one of the bottom electrode and the top electrode having a via portion and a base portion that is formed utilizing a subtractive via etch process. Less via over etching occurs resulting in improved critical dimension control of the bottom and/or top electrodes that are formed by the subtractive via etch process. No bottom liner is present in the MIMCAP thus improving the resistance/capacitance of the device. Also, and in some embodiments, a reduced foot-print area is possible to bring the via portion of the bottom electrode closer to the top electrode.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Yann Mignot, Hsueh-Chung Chen, Junli Wang, Mary Claire Silvestre, Chi-Chun LIU
  • Publication number: 20220406657
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a plurality of metal lines on substrate, forming a sacrificial dielectric material layer between the metal lines, forming a hardmask over at least one of the metal lines, etching at least one of the metal lines that is not covered by the hardmask, treating the sacrificial dielectric material layer to soften the layer. The method also includes removing the treated sacrificial dielectric material layer.
    Type: Application
    Filed: June 18, 2021
    Publication date: December 22, 2022
    Inventors: SOMNATH GHOSH, Karen Elizabeth Petrillo, Cody J. Murray, Ekmini Anuja De Silva, Chi-Chun LIU, Dominik METZLER, John Christopher Arnold