Patents by Inventor Chi-Chung Yu

Chi-Chung Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240104019
    Abstract: Disclosed is a method for enhancing memory utilization and throughput of a computing platform in training a deep neural network (DNN). The critical features of the method includes: calculating a memory size for every operation in a computational graph, storing the operations in the computational graph in multiple groups with the operations in each group being executable in parallel and a total memory size less than a memory threshold of a computational device, sequentially selecting a group and updating a prefetched group buffer, and simultaneously executing the group and prefetching data for a group in the prefetched group buffer to the corresponding computational device when the prefetched group buffer is update. Because of group execution and data prefetch, the memory utilization is optimized and the throughput is significantly increased to eliminate issues of out-of-memory and thrashing.
    Type: Application
    Filed: September 9, 2020
    Publication date: March 28, 2024
    Applicant: AETHERAI IP HOLDING LLC
    Inventors: Chi-Chung CHEN, Wei-Hsiang YU, Chao-Yuan YEH
  • Publication number: 20220309777
    Abstract: System and methods for hemp determination of a cannabis sample are disclosed. The systems and methods may include obtaining headspace data of cannabis samples using a gas chromatography/mass spectrometer (GC/MS) device. The data may then be transformed into images based on retention time, scan range, and signal intensities in the data for assessment by a convolutional network to determine whether a cannabis sample is hemp or non-hemp.
    Type: Application
    Filed: March 28, 2022
    Publication date: September 29, 2022
    Inventor: Chi Chung Yu
  • Publication number: 20220309782
    Abstract: Systems and methods for using a mobile device camera to capture photos of latent fingerprints are disclosed. Various embodiments disclosed implement machine learning and pattern matching algorithms to determine the quality of the captured photo of a latent fingerprint. The quality determined by the algorithms may be used to provide feedback to a user (e.g., a CSI) such that the user can capture higher quality images that improve the reliability in using the fingerprint for search and/or matching.
    Type: Application
    Filed: March 28, 2022
    Publication date: September 29, 2022
    Inventors: Mingkui Wei, Chi Chung Yu
  • Publication number: 20210365651
    Abstract: An identification method of an integrated circuit chip of the present invention includes identifying a surface structure or an internal structure of an integrated circuit chip, generating a structural information set according to the surface structure or internal structure, converting the structural information set into an identification information set. The identification information set generated by the above-mentioned identification method can be stored in a digital file, and a chip manufacturer requires no visible information printed on an outer surface of the integrated circuit chip such that factory information of the integrated circuit chip can be concealed.
    Type: Application
    Filed: September 30, 2020
    Publication date: November 25, 2021
    Inventors: Chi-Chung Yu, Kai-Hung LIN, Tien-Hung LOU
  • Patent number: 11158659
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes an interconnect structure formed over a substrate and a passivation layer formed over the interconnect structure. The semiconductor device structure also includes an anti-acid layer formed in the passivation layer and a bonding layer formed on the anti-acid layer and the passivation layer. The anti-acid layer has a thickness that is greater than about 140 nm.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yin-Shuo Chu, Chi-Chung Yu, Li-Yen Fang, Tain-Shang Chang, Yao-Hsiang Liang, Min-Chih Tsai
  • Publication number: 20180350855
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes an interconnect structure formed over a substrate and a passivation layer formed over the interconnect structure. The semiconductor device structure also includes an anti-acid layer formed in the passivation layer and a bonding layer formed on the anti-acid layer and the passivation layer. The anti-acid layer has a thickness that is greater than about 140 nm.
    Type: Application
    Filed: July 30, 2018
    Publication date: December 6, 2018
    Inventors: Yin-Shuo Chu, Chi-Chung Yu, Li-Yen Fang, Tain-Shang Chang, Yao-Hsiang Liang, Min-Chih Tsai
  • Publication number: 20170170215
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes an interconnect structure formed over a substrate and a passivation layer formed over the interconnect structure. The semiconductor device structure also includes an anti-acid layer formed in the passivation layer and a bonding layer formed on the anti-acid layer and the passivation layer. The anti-acid layer has a thickness that is greater than about 140 nm.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 15, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yin-Shuo CHU, Chi-Chung YU, Li-Yen FANG, Tain-Shang CHANG, Yao-Hsiang LIANG, Min-Chih TSAI
  • Patent number: 9627228
    Abstract: A method for manufacturing a chip package structure having a coating layer is provided. At least one chip package structure is mounted onto a terminal-protection film. The chip package structure has a top side, a back side opposite to the top side and a plurality of lateral sides. A plurality of terminals is disposed on the back side. The terminal-protection film at least partially seals the back side. A coating layer is formed over the top side, the lateral sides and a periphery region of the chip package structure, wherein the coating layer is not formed on the back side and the terminals. The terminal-protection film is debonded from the chip package structure.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: April 18, 2017
    Assignee: Powertech Technology Inc.
    Inventors: Shih-Chun Chen, Sheng-I Huang, Ying-Lin Chen, Ta-Hao Chang, I-Fong Wu, Chi-Chung Yu
  • Patent number: 7605462
    Abstract: A universal substrate includes a plurality of inner pads and a plurality of outer pads. A plurality of bifurcate wirings and a plurality of fuses are formed on a surface of the substrate. The fuses are connected with the bifurcate wirings in series. By the bifurcate wirings and the fuses, each of the inner pads is electrically connected to all of the outer pads to provide optional electrical disconnections therebetween. Accordingly, the universal substrate can provide for various chips with different serial arrangements of bonding pads without replacing or manufacturing another kind of substrate.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: October 20, 2009
    Assignee: Powertech Technology Inc.
    Inventors: Hung-Hsin Hsu, Chi-Chung Yu
  • Publication number: 20080203555
    Abstract: A universal substrate and a semiconductor device utilizing the substrate are disclosed in the present invention. The universal substrate mainly comprises a plurality of inner pads and a plurality of outer pads. A plurality of bifurcate wirings and a plurality of fuses are formed on a surface of the substrate. The fuses are connected with the bifurcate wirings in series. By the bifurcate wirings and the fuses, each of the inner pads is electrically connected to all of the outer pads to provide optional electrical disconnections therebetween. Accordingly, the universal substrate can be utilized for connecting chips having various serial arrangements of bonding pads without replacing or manufacturing another substrate.
    Type: Application
    Filed: February 23, 2007
    Publication date: August 28, 2008
    Inventors: Hung-Hsin Hsu, Chi-Chung Yu
  • Publication number: 20040205366
    Abstract: A method for avoiding data loss in a PDA. The PDA has a RAM, a battery, a central processing unit (CPU), and a nonvolatile accessible memory. The nonvolatile accessible memory has a predetermined region, and the RAM stores user information including global operating system settings. User information is backed up into the predetermined region when remaining power of the battery is lower than a default value. Further, user information from the predetermined region is restored to the RAM when system power is recovered.
    Type: Application
    Filed: March 30, 2004
    Publication date: October 14, 2004
    Inventors: Hung-Chang Hung, Yu-Pao Huang, Liang-Hsin Chien, Chien-Wen Chen, Ming-Chih Hsieh, Chi-Chung Yu