Abstract: A reflective display panel including a pixel array substrate, a color filter substrate, and a liquid crystal layer is provided. The liquid crystal layer is disposed between the pixel array substrate and the color filter substrate. The pixel array substrate includes a first pixel electrode, a second pixel electrode and a third pixel electrode. The second pixel electrode and the third pixel electrode are adjacent to at least one side of the first pixel electrode. In a frame period, a voltage polarity of one of the first pixel electrode, the second pixel electrode, and the third pixel electrode is opposite to voltage polarities of the other two of the first pixel electrode, the second pixel electrode, and the third pixel electrode. Three of multiple filter patterns of the color filter substrate respectively overlapping the first pixel electrode, the second pixel electrode, and the third pixel electrode have different filter colors.

Abstract: A semiconductor device includes a gate structure on a semiconductor fin, a dielectric layer on the gate structure, and a gate contact extending through the dielectric layer to the gate structure. The gate contact includes a first conductive material on the gate structure, a top surface of the first conductive material extending between sidewalls of the dielectric layer, and a second conductive material on the top surface of the first conductive material.

Abstract: A USB device includes a base, a circuit board disposed on the base and having front-end and rear-end portions and a ground circuitry, an upper cover, solder points, a switch and a button mount. The rear-end portion is used for inserting into a connection port of a computer terminal. The upper cover covers the front-end portion and has an opening. The solder points are formed on the front-end portion and coupled to the ground circuitry. The switch having a metal cover is soldered to the solder points for controlling wireless connection between the computer terminal and an external device. The button mount is movably disposed through the opening and sleeves the front-end portion for triggering the switch. An electrostatic discharge entering from the opening can pass through a first guide hole of the button mount and is conducted to the ground circuitry via the metal cover and the solder point.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate including an element isolation structure defining first to third active regions and first to third elements respectively in the first to third active region. The first element includes a first gate dielectric layer embedded in the first active region of the substrate and isolation structures embedded in the substrate at opposite sides of the first gate dielectric layer. Bottom surfaces of the isolation structures include first portions at the same level as a bottom surface of the element isolation structure and second portions being oblique with respective to the first portions.

Abstract: A display device with a rotatable camera is provided. In one example, the display device may include a housing. The display device may include a screen configured to display information to a user. The display device may include a camera mounted in the housing and configured to rotate relative to the housing, in response to a manipulation by the user, between an exposed orientation wherein the camera is configured to capture images of the user, and a concealed orientation wherein the camera is obscured from capturing images of the user. Additional devices, systems, and methods are also provided.

Abstract: A die stack includes: a first die including a first semiconductor substrate; a first redistribution layer (RDL) structure disposed on a front surface of the first die and electrically connected to the first semiconductor substrate; a second die bonded to the front surface of the first die and including a second semiconductor substrate; a third die bonded to the front surface of the first die and including a third semiconductor substrate; a second RDL structure disposed on front surfaces of the second and third dies and electrically connected to the second and third semiconductor substrates; and a through dielectric via (TDV) structure extending between the second and third dies and electrically connected to the first RDL structure and second RDL structure. The second and third dies are disposed in a plane that extends perpendicular to a vertical stacking direction of the die stack.

Abstract: The present disclosure provides an integrated circuit (IC) structure that includes an IC packaging structure having an IC chip; and a thermoelectric self-cooling device (TESCD) integrated with the IC packaging structure. The TESCD further includes a thermoelectric cooling (TEC) device having a plurality of TEC units configured in an array and electrically connected to provide cooling effect to the IC packaging structure, and a liquid cooling module having a cooling liquid driving device and a generator coupled with the cooling liquid driving device to collectively generate an electrical power supplied to the TEC device with self-cooling function to the IC packaging structure.

Abstract: A liquid cooling system includes a thermoelectric cooler (TEC) between a radiator plate and a radiator, and a thermoelectric generator (TEG) at a location where the TEG is driven by heat from a chip package. The chip package is cooled by a cold plate of the liquid cooling system and the TEC is controlled by the TEG. The TEG may be between the chip package and the cold plate or elsewhere in or adjacent to the chip package. The TEG may control the TEC through a relay. The TEG automatically activates the TEC when the chip package is under peak load.

Abstract: A package structure includes a high-power package attached to a substrate; a first low-power package attached to the substrate; a first heat dissipation device attached to the first low-power package; a liquid cooling system attached to the high-power package; and a thermoelectric system sandwiched between the high-power package and the liquid cooling system, wherein the thermoelectric system is electrically connected to the first heat dissipation device, wherein the thermoelectric system provides the first heat dissipation device with electrical power during operation of the high-power package.

Abstract: A die includes: a semiconductor substrate having a front side and an opposing back side; a dielectric structure including a substrate oxide layer disposed on the front side of the semiconductor substrate and interlayer dielectric (ILD) layers disposed on the substrate oxide layer; an interconnect structure disposed in the dielectric structure; a through-silicon via (TSV) structure extending in a vertical direction from the back side of the semiconductor substrate through the front side of the semiconductor substrate, such that a first end of the TSV structure is disposed in the interconnect structure; and a TSV barrier structure including a barrier line that contacts the first end of the TSV structure, and a first seal ring disposed in the substrate oxide layer and that surrounds the TSV structure in a lateral direction perpendicular to the vertical direction.

Abstract: An encapsulation structure is provided. The encapsulation structure includes a flexible substrate that has an element area and a non-element area. The encapsulation structure also includes multiple electronic elements disposed in the element area. The encapsulation structure further includes multiple light-guiding structures disposed on the electronic elements. The light-guiding structure includes a convex structure and/or a concave structure. The convex structure, in a cross-section, has at least one curved surface, at least two inclined surfaces, or a combination of at least one curved surface and one inclined surface. The concave structure, in a cross-section, has at least one curved surface or at least two inclined surfaces.

Abstract: An integrated circuit package and the method of forming the same are provided. An integrated circuit package may include a first die having a first substrate over a package substrate and a lid. A first channel may extend through the first substrate from a first sidewall of the first die to a second sidewall of the first die. The lid may include a top portion over the first die and a first bottom portion extending along the first sidewall of the first die. The first bottom portion may include a second channel connected to the first channel.

Abstract: A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.

Abstract: A control assembly configured for an electronic device, the control assembly includes a mount seat configured to be installed on the electronic device, two first connection components movably connected to the mount seat, two second connection component movably connected to the two first connection components, respectively, two controllers configured to communicate with the electronic device, the two controllers are separated apart from each other and movably connected to the second connection components, respectively, such that the two controllers are connected to the mount seat via the two second connection components and the two first connection components.

Abstract: This invention discloses a display panel includes a substrate and a sub-pixel. The sub-pixel is disposed on the substrate. The sub-pixel includes a transistor, and the transistor includes a gate, a semiconductor layer, a source, a drain, and a dummy electrode. The gate is disposed on the substrate. The semiconductor layer is disposed on the gate. The source and the drain are disposed on the semiconductor layer, the source is disposed at one end of the semiconductor layer, and the drain is disposed at the other end of the semiconductor layer. The dummy electrode is disposed on the semiconductor layer and between the source and the drain. The dummy electrode and the source are separated, the dummy electrode and the drain are separated, and the dummy electrode is electrically floating.

Abstract: A die includes: a semiconductor substrate having a front side and an opposing backside; a dielectric structure including a substrate oxide layer disposed on the front side of the semiconductor substrate and interlayer dielectric (ILD) layers disposed on the substrate oxide layer; an interconnect structure disposed in the dielectric structure; a through-silicon via (TSV) structure extending in a vertical direction from the backside of the semiconductor substrate through the front side of the semiconductor substrate, such that a first end of the TSV structure is disposed in the interconnect structure; and a TSV barrier structure including a barrier line that contacts the first end of the TSV structure, and a first seal ring disposed in the substrate oxide layer and that surrounds the TSV structure in a lateral direction perpendicular to the vertical direction.

Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE receives a CORESET configuration specifying one or more properties of a first CORESET. The UE also determines time and frequency resource elements of the first CORESET based on the one or more properties. The UE performs blind decoding on down-link control channel candidates in a search space carried by the first CORESET to obtain a down-link control channel.

Abstract: Systems and methods for communicating data via a multilane data link from a first clock domain to a second clock domain, where the data streams of a multilane link are clocked into FIFO deskew buffers using clock signals that are recovered from the data streams themselves. Each data stream is clocked into the deskew buffer with the clock signal recovered from that data stream. The data is clocked out of the deskew buffers using the clock signal of a target clock domain so that the data streams clocked out of the deskew buffers are synchronized with each other and with the clock signal of the target clock domain (the target clock signal) to eliminate the need for a separate clock domain crossing buffer.

Abstract: A beam switching system, beam switching method, and antenna device are provided. The beam switching system includes a selection circuit and a branch line coupler. The selection circuit includes an input port for receiving the input radio frequency signal and two output ports. The selection circuit selects at least one of its two output ports to output the output radio frequency signal. The branch line coupler includes two input ports respectively coupled to two output ports of the selection circuit and used to receive the output radio frequency signal, and two output ports respectively used to couple two antennas.