Abstract: A semiconductor device includes a logic circuit region having at least one core device and at least one input/output (I/O) device. The at least one core device has a first accumulative antenna ratio, and the at least one I/O device has a second accumulative antenna ratio. The first accumulative antenna ratio is greater than the second accumulative antenna ratio.

Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.

Abstract: A method of detecting surface pressure distribution of a wafer being processed by a CMP (Chemical Mechanical Polishing) process; more specifically, the invention relates to a method of detecting pressure distribution of a wafer surface by employing pressure sensitive films located on various pressure components such as a wafer carrier, a polishing pad, and mechanical arm members of a CMP machine for detecting pressure-related data during different stages of a CMP process. Further, sensed pressure-related data are collected for feedback loop controls of digital image mapping, numeration, simulation, and forecasting, from which more mechanical components of high precision and better circuit layouts on the wafer can then be developed.

Abstract: A scribe line structure of a semiconductor wafer is provided in the invention. The semiconductor wafer has a plurality of substantially parallel horizontal scribe lines and a plurality of substantially parallel vertical scribe lines to separate a plurality of chips from each other. According to the invention, each parallel horizontal scribe line and each parallel vertical scribe line are divided along two elongated sides thereof into a plurality of portions with the same rectangular area. Each of the plurality of portions of each scribe line is composed of the scribe line structure. The scribe line structure comprises a multi-layer structure with four sides formed over whole area of each portion of each scribe line and at least two rows of cavities formed along the four sides of the multi-layer structure. The cavities of the scribe line structure are capable of relieving internal stress of the scribe lines and arresting possible cracks induced during scribe line manufacture.

Abstract: A scribe line structure of a semiconductor wafer is provided in the invention. The semiconductor wafer has a plurality of substantially parallel horizontal scribe lines and a plurality of substantially parallel vertical scribe lines to separate a plurality of chips from each other. According to the invention, each parallel horizontal scribe line and each parallel vertical scribe line are divided along two elongated sides thereof into a plurality of portions with the same rectangular area. Each of the plurality of portions of each scribe line is composed of the scribe line structure. The scribe line structure comprises a multi-layer structure with four sides formed over whole area of each portion of each scribe line and at least two rows of cavities formed along the four sides of the multi-layer structure. The cavities of the scribe line structure are capable of relieving internal stress of the scribe lines and arresting possible cracks induced during scribe line manufacture.

Abstract: A manufacturing method and a structure of a multi-layered dielectric layer for forming openings in the direction layers for improving integration of integrated circuits, capability of step coverage, and problems caused by a structure of overhang, in which oblique sidewalls of the openings in multi-layered dielectric layer can improve the step coverage in the following manufacturing process.

Abstract: An inter-metal dielectric (IMD) layer structure and its forming method are disclosed. The IMD layer structure is formed between a first conducting layer and a second conducting layer and includes a first dielectric layer overlying the first conducting layer, a glass layer overlying the first dielectric layer, an etching stop layer overlying the glass layer, and a second dielectric layer overlying the etching stop layer under the second conducting layer. The etching rate of the etching stop layer is relatively low so that it can prevent the glass layer etched out. Therefore, a long-time etching can be used to obtain a better through hole profile.

Abstract: A manufacturing method and a structure of a multi-layered dielectric layer for forming openings in the dielectric layers for improving integration of integrated circuits, capability of step coverage, and problems caused by a structure of overhang, in which oblique sidewalls of the openings in multi-layered dielectric layer can improve the step coverage in the following manufacturing process.

Abstract: An interconnect structure for use in semiconductor devices, comprising: (a) a thin and elongated aluminum wire connected to a first metal structure; and (b) a plurality of regularly spaced dummy tungsten plugs which are connected to the aluminum wire at one end and are buried in an underlying dielectric layer so that it is insulated at the other end. The dummy tungsten plugs absorb the mobile aluminum atoms generated through stress-induced migration when the interconnect structure is subject to a rapid temperature change, thus preventing the via bulging problem which could seriously damage the second metal structure above the first metal structure.

Abstract: A method for fabricating funnel-shaped vias in semiconductor devices with an improved profile amelioration of the sharp angles at the onset of the via and at the intersection between the wet etch section (i.e., the bowl-shaped section) and the dry etch section (i.e., the straight section).

Abstract: A process for forming shallow trench isolation (STI) structures. It includes the steps of: (a) depositing a composite silicon nitride on to the silicon substrate; (b) forming a shallow trench on the silicon substrate by etching, using the composite silicon nitride as the hard mask; (c) depositing a filler oxide layer inside the shallow trench as well as on top of the composite silicon nitride, using a chemical vapor deposition (CVD) method; and (d) using a chemical-mechanical polishing (CMP) process to planarize the filler oxide layer using the composite nitride as a CMP stop. The composite silicon nitride comprises a plurality of silicon nitride layers whose CMP removal rate increases with the distance from the silicon substrate. Additionally, a composite silicon oxide layer can be formed on top of the filler oxide layer which comprises a plurality of silicon oxide layers whose CMP removal rate increases with the distance from the silicon substrate.

Abstract: A heating assembly for use in semiconductor fabrication processes to evaporate solvent contained in a liquefied spin-on-glass (SOG) layer so as cause the SOG layer to solidify. The heating assembly contains: (a) a hot plate and a loader robot to transport a semiconductor wafer to a surface of the hot plate; (b) a plurality of through holes formed in the hot plate; (c) a plurality of movable support columns traveling through the through holes to support the semiconductor wafer and allow the semiconductor wafer to descend in a controlled manner; and (d) a controller to control a descending speed of the plurality of movable support columns. By carefully controlling the descending speed of the liquefied SOG-containing wafer, the formation of micro-cracks can be eliminated, thus resulting in improved yield rate.

Abstract: A manufacturing method and a structure of a multi-layered dielectric layer for forming openings in the dielectric layers for improving integration of integrated circuits, capability of step coverage, and problems caused by a structure of overhang, in which oblique sidewalls of the openings in multi-layered dielectric layer can improve the step coverage in the following manufacturing process.

Abstract: An improved metal bonding pad is disclosed which can prevent the formation of cracks during the high temperature PECVD deposition, and the subsequent annealing, of a passivation layer which is formed to encroach the metal bonding pad and provide an encapsulation force on the metal bonding pad. The metal bonding pad comprises a plurality of stress bumpers on the periphery thereof. The stress bumpers can be hollow elongated round-cornered rectangles, pin-shaped circles, Y-shaped polygons, or ellipses. The stress bumpers, which create a discontinuous structure in the metal pad, can effectively stop stress propagation as well as relieve and re-direct stress propagation, so as to maintain the integrity of the passivation encroachment and prevent the peeling off problems often observed with the metal bonding pad.

Abstract: A method for chemically-and-mechanically polishing a semiconductor wafer surface is disclosed. It includes the steps of: (a) providing a mechanical polishing pad; (b) placing a pressure-sensitive film on top of a wafer surface to be polished by the mechanical polishing pad, the pressure-sensitive film contains materials that will show pressure-dependent colors when subject to an external pressure; (c) commencing a chemically-and-mechanically polishing process so that the mechanical polishing pad exerts a pressure on the pressure-sensitive film; (d) scanning the pressure-dependent color pattern on the pressure-sensitive film; (e) converting the pressure-dependent color pattern into a pressure distribution; and (f) adjusting the mechanical polishing pad, or a leveling of the wafer mounting, or both, according to the pressure distribution obtained in step (e).

Abstract: A wafer planarization process which utilizes combined high density plasma chemical vapor deposition (HDP-CVD) process and chemical mechanical polishing (CMP) process is disclosed. This process includes the steps of (a) forming a first HDP-CVD layer on the surface of a semiconductor wafer using a first HDP-CVD composition having a higher etching/depositing component ratio and thus a lower CMP removal rate; (b) forming a second HDP-CVD layer on the first HDP-CVD layer using the same HDP-CVD process but with a second HDP-CVD composition having a highest etching/depositing component ratio and thus the lowest CMP removal rate; (c) forming a third HDP-CVD layer on the second HDP-CVD layer using the same HDP-CVD process but with a third HDP-CVD composition having a low etching/depositing component ratio and thus a high CMP removal rate; and (d) using a chemical mechanical process to remove at least a part of the third HDP-CVD layer using the second HDP-CVD layer as a stopper.

Abstract: A wafer planarization process which utilizes combined high density plasma chemical vapor deposition (HDP-CVD) process and chemical mechanical polishing (CMP) process is disclosed. This process includes the steps of (a) forming a first HDP-CVD layer on the surface of a semiconductor wafer using a first HDP-CVD composition having a higher etching/depositing component ratio and thus a lower CMP removal rate; (b) forming a second HDP-CVD layer on the first HDP-CVD layer using the same HDP-CVD process but with a second HDP-CVD composition having a highest etching/depositing component ratio and thus the lowest CMP removal rate; (c) forming a third HDP-CVD layer on the second HDP-CVD layer using the same HDP-CVD process but with a third HDP-CVD composition having a low etching/depositing component ratio and thus a high CMP removal rate; and (d) using a chemical mechanical process to remove at least a part of the third HDP-CVD layer using the second HDP-CVD layer as a stopper.

Abstract: A wafer planarization process which utilizes combined high density plasma chemical vapor deposition (HDP-CVD) process and chemical mechanical polishing (CMP) process is disclosed. This process includes the steps of (a) forming a first HDP-CVD layer on the surface of a semiconductor wafer using a first HDP-CVD composition having a higher etching/depositing component ratio and thus a lower CMP removal rate; (b) forming a second HDP-CVD layer on the first HDP-CVD layer using the same HDP-CVD process but with a second HDP-CVD composition having a lower etching/depositing component ratio and thus a higher CMP removal rate; and (c) using a chemical mechanical process to remove at least a part of the second HDP-CVD layer using the first HDP-CVD layer as a stopper. A protective layer with the same etching/deposition components but a different ratio than the sacrificial layer can be deposited on the sacrificial layer to minimize the dishing effect during the initial stage of the chemical mechanical polishing process.