Patents by Inventor Chi-Fan Yung

Chi-Fan Yung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240291483
    Abstract: A circuit for driving output of a capacitive element between two voltage levels has at least one driver cell with a first switch pair connected in series between a first voltage source terminal and the capacitive element and a second switch pair connected in series between a second voltage source terminal and the capacitive element. One or more non-dissipative elements may be connected between a first common node of the first switch pair and a second common node of the second switch pair. Combinations of driver cell switches are activated and deactivated in sequences to provide step-wise transfer of energy to the capacitive element, subtracting from an input voltage, bypassing a driver cell, and adding to the input voltage. Switching stages to reach a high voltage output may be identical to but organized in reverse order from the switching stages to reach a low voltage output.
    Type: Application
    Filed: March 6, 2024
    Publication date: August 29, 2024
    Inventors: Tsz Yin Man, Chi Fan YUNG, Bruce C. LARSON
  • Patent number: 11955962
    Abstract: A circuit for driving the voltage of a capacitive element between two voltage levels has at least one driver cell with a first pair of switches connected in series between a first terminal of a voltage source and the capacitive element, and a second pair of switches connected in series between a second terminal of the voltage source and the capacitive element. A plurality of non-dissipative elements may be connected in parallel or in series between the first pair of switches and the second pair of switches. Combinations of switches from the driver cells may be activated and deactivated in a defined sequence to provide step-wise transfer of energy to the capacitive element. The defined sequence may have a switching pattern with a voltage change portion arranged to cause a change in an output voltage of the capacitive element driver during application thereof on the capacitive element driver.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: April 9, 2024
    Assignee: NEOLITH LLC
    Inventors: Tsz Yin Man, Chi Fan Yung, Bruce C. Larson
  • Publication number: 20230231553
    Abstract: A circuit for driving the voltage of a capacitive element between two voltage levels has at least one driver cell with a first pair of switches connected in series between a first terminal of a voltage source and the capacitive element, and a second pair of switches connected in series between a second terminal of the voltage source and the capacitive element. A plurality of non-dissipative elements may be connected in parallel or in series between the first pair of switches and the second pair of switches. Combinations of switches from the driver cells may be activated and deactivated in a defined sequence to provide step-wise transfer of energy to the capacitive element. The defined sequence may have a switching pattern with a voltage change portion arranged to cause a change in an output voltage of the capacitive element driver during application thereof on the capacitive element driver.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 20, 2023
    Inventors: Tsz Yin MAN, Chi Fan YUNG, Bruce C. LARSON
  • Patent number: 11575376
    Abstract: A circuit for driving the voltage of a capacitive element between two voltage levels has at least one driver cell with a first pair of switches connected in series between a first terminal of a voltage source and the capacitive element, and a second pair of switches connected in series between a second terminal of the voltage source and the capacitive element. One or more non-dissipative elements may be connected between the common node of the first pair of switches and the common node of the second pair of switches. Combinations of switches from the driver cells may be activated and deactivated in a defined sequence to provide step-wise transfer of energy to the capacitive element. In one sequence, switches in a selected driver cell may subtract a specified voltage from an input voltage, bypass the selected driver cell, and add the specified voltage to the input voltage.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 7, 2023
    Assignee: NEOLITH LLC
    Inventors: Tsz Yin Man, Chi Fan Yung, Bruce C. Larson
  • Patent number: 11009901
    Abstract: Certain aspects of the present disclosure generally relate a regulator. For example, the regulator may include a control stage, a sense capacitor having first and second terminals, the first terminal coupled to an output of the voltage regulator, and a current amplifier having an input coupled to the second terminal of the sense capacitor and an output coupled to the control stage. The control stage of the regulator may adjust the output voltage of the regulator based at least in part on a current generated by the current amplifier.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: May 18, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Chi Fan Yung, Hua Guan, Ngai Yeung Ho, Kan Li
  • Publication number: 20210099171
    Abstract: A circuit for driving the voltage of a capacitive element between two voltage levels has at least one driver cell with a first pair of switches connected in series between a first terminal of a voltage source and the capacitive element, and a second pair of switches connected in series between a second terminal of the voltage source and the capacitive element. One or more non-dissipative elements may be connected between the common node of the first pair of switches and the common node of the second pair of switches. Combinations of switches from the driver cells may be activated and deactivated in a defined sequence to provide step-wise transfer of energy to the capacitive element. In one sequence, switches in a selected driver cell may subtract a specified voltage from an input voltage, bypass the selected driver cell, and add the specified voltage to the input voltage.
    Type: Application
    Filed: September 25, 2020
    Publication date: April 1, 2021
    Inventors: Tsz Yin MAN, Chi Fan YUNG, Bruce C. LARSON
  • Patent number: 10651799
    Abstract: Certain aspects of the present disclosure provide methods and apparatus for generating an envelope tracking power supply voltage. For example, certain aspects of the present disclosure provide an envelope tracking power supply having a linear amplifier having an output coupled to a power supply node of an amplifier, wherein a power supply node of the linear amplifier is coupled to a first voltage supply node. The envelope tracking power supply may also include a switch mode power supply having an output coupled to the power supply node of the amplifier. Certain aspects also include a circuit having a first switch coupled to the first voltage supply node and a second switch coupled to a second voltage supply node, wherein a power supply node of the switch mode power supply is coupled to the first switch and the second switch.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 12, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Zhiqing Zhang, Chi Fan Yung, Joseph Duncan, Jun Hua, Song Shi, Thomas Marra
  • Patent number: 10615796
    Abstract: Certain aspects of the present disclosure provide methods and apparatus for level shifting an input signal ranging between certain voltage levels to generate an output signal ranging between other voltage levels with low power, high speed, and immunity to noise. One example level-shifting circuit generally includes a node for receiving an input signal ranging between a first voltage level and a second voltage level, a first circuit path coupled to the node and configured to level shift the input signal to generate an output signal ranging between a third voltage level and a fourth voltage level, a pulse generator coupled to the node and configured to generate a pulse based on a transition in the input signal between the first and second voltage levels, and a second circuit path connected in parallel with the first path and configured to temporarily short the first path based on the generated pulse.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: April 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Zhiqing Zhang, Brett Walker, Chi Fan Yung, Justin Philpott, Joseph Duncan
  • Publication number: 20190326858
    Abstract: Certain aspects of the present disclosure provide methods and apparatus for generating an envelope tracking power supply voltage. For example, certain aspects of the present disclosure provide an envelope tracking power supply having a linear amplifier having an output coupled to a power supply node of an amplifier, wherein a power supply node of the linear amplifier is coupled to a first voltage supply node. The envelope tracking power supply may also include a switch mode power supply having an output coupled to the power supply node of the amplifier. Certain aspects also include a circuit having a first switch coupled to the first voltage supply node and a second switch coupled to a second voltage supply node, wherein a power supply node of the switch mode power supply is coupled to the first switch and the second switch.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 24, 2019
    Inventors: Zhiqing ZHANG, Chi Fan YUNG, Joseph DUNCAN, Jun HUA, Song SHI, Thomas MARRA
  • Patent number: 10340854
    Abstract: Certain aspects of the present disclosure provide methods and apparatus for generating an envelope tracking power supply voltage. For example, certain aspects of the present disclosure provide an envelope tracking power supply having a linear amplifier having an output coupled to a power supply node of an amplifier, wherein a power supply node of the linear amplifier is coupled to a first voltage supply node. The envelope tracking power supply may also include a switch mode power supply having an output coupled to the power supply node of the amplifier. Certain aspects also include a circuit having a first switch coupled to the first voltage supply node and a second switch coupled to a second voltage supply node, wherein a power supply node of the switch mode power supply is coupled to the first switch and the second switch.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: July 2, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Zhiqing Zhang, Chi Fan Yung, Joseph Duncan, Jun Hua, Song Shi, Thomas Marra
  • Publication number: 20190146531
    Abstract: Certain aspects of the present disclosure generally relate a regulator. For example, the regulator may include a control stage, a sense capacitor having first and second terminals, the first terminal coupled to an output of the voltage regulator, and a current amplifier having an input coupled to the second terminal of the sense capacitor and an output coupled to the control stage. The control stage of the regulator may adjust the output voltage of the regulator based at least in part on a current generated by the current amplifier.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 16, 2019
    Inventors: Chi Fan YUNG, Hua GUAN, Ngai Yeung HO, Kan LI
  • Patent number: 10274986
    Abstract: An integrated circuit is disclosed for current-controlled voltage regulation. In an example aspect, the integrated circuit includes a voltage regulator and a current-controlled clamp. The voltage regulator has a regulator output node and produces a regulator current. The voltage regulator includes an error amplifier and an output transistor. The error amplifier has first and second input nodes and an error amplifier output node, with the first input node coupled to a reference voltage. The error amplifier generates an error amplifier output voltage at the output node. The output transistor is coupled between the error amplifier output node and the regulator output node. The output transistor is coupled to the second input node via the regulator output node to establish a feedback path for the voltage regulator. The current-controlled clamp is coupled to the error amplifier output node and clamps the error amplifier output voltage based on the regulator current.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: April 30, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Chi Fan Yung, Xiaodan Zou, Ngai Yeung Ho, Hua Guan, Kan Li
  • Publication number: 20180284830
    Abstract: An integrated circuit is disclosed for current-controlled voltage regulation. In an example aspect, the integrated circuit includes a voltage regulator and a current-controlled clamp. The voltage regulator has a regulator output node and produces a regulator current. The voltage regulator includes an error amplifier and an output transistor. The error amplifier has first and second input nodes and an error amplifier output node, with the first input node coupled to a reference voltage. The error amplifier generates an error amplifier output voltage at the output node. The output transistor is coupled between the error amplifier output node and the regulator output node. The output transistor is coupled to the second input node via the regulator output node to establish a feedback path for the voltage regulator. The current-controlled clamp is coupled to the error amplifier output node and clamps the error amplifier output voltage based on the regulator current.
    Type: Application
    Filed: September 22, 2017
    Publication date: October 4, 2018
    Inventors: Chi Fan Yung, Xiaodan Zou, Ngai Yeung Ho, Hua Guan, Kan Li
  • Publication number: 20180136680
    Abstract: A voltage regulator control implementation dynamically detects and sets specified headroom for a low dropout (LDO) regulator at different loads to enable the LDO regulator to maintain high performance in conjunction with improved power efficiency. In one instance, an upstream voltage regulator may adaptively adjust an output voltage supplied to an input supply rail of a downstream LDO regulator based on an indication from the LDO regulator. The adaptively adjusted input voltage enables the downstream LDO regulator to achieve high performance and improved power efficiency across the entire range of load conditions.
    Type: Application
    Filed: December 26, 2017
    Publication date: May 17, 2018
    Inventors: Mengmeng DU, Hua GUAN, Ngai Yeung HO, Chi Fan YUNG
  • Publication number: 20180107232
    Abstract: Certain aspects of the present disclosure generally relate a dual feedback loop regulator. For example, the regulator may include a first amplifier having an output coupled to an output node of the regulator, the output node further coupled to a first feedback path and a second feedback path of the regulator. A first input of a second amplifier may be coupled to the first feedback path and a second input of the second amplifier may be coupled to a reference path. The regulator may also include a transconductance stage having a first transistor and a first current source, the first transistor and the current source coupled to the first feedback path and the second feedback path, and a transimpedance stage coupled to the transconductance stage and an input of the first amplifier.
    Type: Application
    Filed: October 18, 2016
    Publication date: April 19, 2018
    Inventors: Chi Fan YUNG, Xiaodan ZOU, Ngai Yeung HO, Kan LI, Hua GUAN
  • Patent number: 9946283
    Abstract: Certain aspects of the present disclosure generally relate a dual feedback loop regulator. For example, the regulator may include a first amplifier having an output coupled to an output node of the regulator, the output node further coupled to a first feedback path and a second feedback path of the regulator. A first input of a second amplifier may be coupled to the first feedback path and a second input of the second amplifier may be coupled to a reference path. The regulator may also include a transconductance stage having a first transistor and a first current source, the first transistor and the current source coupled to the first feedback path and the second feedback path, and a transimpedance stage coupled to the transconductance stage and an input of the first amplifier.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: April 17, 2018
    Assignee: Qualcomm Incorporated
    Inventors: Chi Fan Yung, Xiaodan Zou, Ngai Yeung Ho, Kan Li, Hua Guan
  • Patent number: 9886048
    Abstract: A voltage regulator control implementation dynamically detects and sets specified headroom for a low dropout (LDO) regulator at different loads to enable the LDO regulator to maintain high performance in conjunction with improved power efficiency. In one instance, an upstream voltage regulator may adaptively adjust an output voltage supplied to an input supply rail of a downstream LDO regulator based on an indication from the LDO regulator. The adaptively adjusted input voltage enables the downstream LDO regulator to achieve high performance and improved power efficiency across the entire range of load conditions.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: February 6, 2018
    Assignee: Qualcomm Incorporated
    Inventors: Mengmeng Du, Hua Guan, Ngai Yeung Ho, Chi Fan Yung
  • Publication number: 20180034415
    Abstract: Certain aspects of the present disclosure provide methods and apparatus for generating an envelope tracking power supply voltage. For example, certain aspects of the present disclosure provide an envelope tracking power supply having a linear amplifier having an output coupled to a power supply node of an amplifier, wherein a power supply node of the linear amplifier is coupled to a first voltage supply node. The envelope tracking power supply may also include a switch mode power supply having an output coupled to the power supply node of the amplifier. Certain aspects also include a circuit having a first switch coupled to the first voltage supply node and a second switch coupled to a second voltage supply node, wherein a power supply node of the switch mode power supply is coupled to the first switch and the second switch.
    Type: Application
    Filed: July 6, 2017
    Publication date: February 1, 2018
    Inventors: Zhiqing ZHANG, Chi Fan YUNG, Joseph DUNCAN, Jun HUA, Song SHI, Thomas MARRA
  • Publication number: 20180034466
    Abstract: Certain aspects of the present disclosure provide methods and apparatus for level shifting an input signal ranging between certain voltage levels to generate an output signal ranging between other voltage levels with low power, high speed, and immunity to noise. One example level-shifting circuit generally includes a node for receiving an input signal ranging between a first voltage level and a second voltage level, a first circuit path coupled to the node and configured to level shift the input signal to generate an output signal ranging between a third voltage level and a fourth voltage level, a pulse generator coupled to the node and configured to generate a pulse based on a transition in the input signal between the first and second voltage levels, and a second circuit path connected in parallel with the first path and configured to temporarily short the first path based on the generated pulse.
    Type: Application
    Filed: July 25, 2017
    Publication date: February 1, 2018
    Inventors: Zhiqing ZHANG, Brett WALKER, Chi Fan YUNG, Justin PHILPOTT, Joseph DUNCAN
  • Publication number: 20170322575
    Abstract: A voltage regulator control implementation dynamically detects and sets specified headroom for a low dropout (LDO) regulator at different loads to enable the LDO regulator to maintain high performance in conjunction with improved power efficiency. In one instance, an upstream voltage regulator may adaptively adjust an output voltage supplied to an input supply rail of a downstream LDO regulator based on an indication from the LDO regulator. The adaptively adjusted input voltage enables the downstream LDO regulator to achieve high performance and improved power efficiency across the entire range of load conditions.
    Type: Application
    Filed: September 2, 2016
    Publication date: November 9, 2017
    Inventors: Mengmeng DU, Hua GUAN, Ngai Yeung HO, Chi Fan YUNG