Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: A probe head includes multiple probes and guide plates. Each probe includes a first end, a second end, and a probe body. The first end abuts a contact pad of a device under test. The second end abuts a contact pad of a board of a probe system. The probe body extends between the first end and the second end according to a longitudinal development axis. The guide plate includes a guide-hole pair for a probe pair of the probe head to respectively pass through, and the guide-hole pair slidably accommodate the pair of probes. The guide plate further includes an extension hole extending from one guide hole of the guide-hole pair to another guide hole. The extension hole intersects with at least one of the first guide holes and is located substantially between the probe pair on the first guide plate.

Abstract: A probe system and a probe card, a probe head and a guide plate structure thereof are described herein. The probe head includes a plurality of probes and guide plates. Each probe includes a first end, a second end, and a probe body. The first end is configured to abut a contact pad of the device under test. The second end is configured to abut a contact pad of a board of the probe system. The probe body extends between the first end and the second end according to a longitudinal development axis. The guide plate includes a pair of first guide holes for a pair of probes to pass through, and the pair of first guide holes are configured to slidably accommodate the pair of probes. The material between the pair of first guide holes in the guide plate has a relative dielectric constant not greater than 6, so as to reduce the return loss between the probe head and the device under test.

Abstract: A probe head includes multiple probes and guide plates. Each probe includes a first end, a second end, and a probe body. The first end abuts a contact pad of a device under test. The second end abuts a contact pad of a board of a probe system. The probe body extends between the first end and the second end according to a longitudinal development axis. The guide plate includes a guide-hole pair for a probe pair of the probe head to respectively pass through, and the guide-hole pair slidably accommodate the pair of probes. The guide plate further includes an extension hole extending from one guide hole of the guide-hole pair to another guide hole to provide compensating impedance between the guide-hole pair, improve impedance matching when probing the device under test with the probe pair, and reduce return loss between the probe head and the device under test.

Abstract: A memory with built-in synchronous-write-through (SWT) redundancy includes a plurality of memory input/output (IO) arrays, a plurality of SWT circuits, and at least one spare SWT circuit. The at least one spare SWT circuit is used to replace at least one of the plurality of SWT circuits that is defective.

Abstract: A semiconductor device includes a first gate stack structure over a substrate, a source/drain epitaxial layer, a lightly doped region, and a silicide region. The source/drain epitaxial layer is disposed in the substrate and adjacent to the first gate stack structure. The lightly doped region is located in the substrate to be electrically connected to the source/drain epitaxial layer. The lightly doped region includes a first portion protrudes from a sidewall of the source/drain epitaxial layer. The silicide region is in contact with a top surface and sidewalls of a top portion of the source/drain epitaxial layer and a top surface of the first portion of the lightly doped region. The top portion of the source/drain epitaxial layer is higher than the top surface of the first portion of the lightly doped region.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: A video decoder for decoding a composite video signal. The decoder includes an analog-to-digital converter (ADC), an input resampler, and a Y/C separator, all coupled in series. The ADC receives and digitizes the composite video signal to generate ADC samples. The input resampler receives and resamples the ADC samples with a first resampling signal to generate resampled video samples. The Y/C separator receives and separates the resampled video samples into luminance and chrominance components. The Y/C separator includes a delay element configured to receive the resampled video samples and provide a variable amount of delay. The variable amount of delay can be adjustable from line to line, and is typically based on an approximated duration of a video line.

Abstract: Techniques for enhancing edges in video signals while reducing the amounts of undershoots and overshoots. A video signal is processed to generate a first signal indicative of detected edges in the video signal. The first signal can be generated by lowpass filtering the video signal to generate a lowpass signal and subtracting the lowpass signal from a luminance signal that has been extracted from the video signal. The first signal is then processed with a “non-linear” transfer function to generate a second signal having enhanced edges. The second signal is used as the correction or enhancement signal, and is added to the lowpass signal to provide an output signal having enhanced edges with reduced or minimal amounts of undershoots and overshoots.