Abstract: A semiconductor device includes a logic circuit region having at least one core device and at least one input/output (I/O) device. The at least one core device has a first accumulative antenna ratio, and the at least one I/O device has a second accumulative antenna ratio. The first accumulative antenna ratio is greater than the second accumulative antenna ratio.

Abstract: In some embodiments of the present disclosure, a sustained release osmotic-controlled pharmaceutical composition is provided, including: a core and a semi-permeable membrane coated on the core. The core includes a drug compartment, in which the drug compartment includes a first active ingredient, a first polymer and a first osmogen, and the first active ingredient includes lurasidone, a pharmaceutical acceptable salt of the lurasidone or a combination thereof. The semi-permeable membrane includes a membrane body and at least one pore distributed in the membrane body.

Abstract: A device includes a first channel layer, a second channel layer, a gate structure, a source/drain epitaxial structure, and a source/drain contact. The first channel layer and the second channel layer are arranged above the first channel layer in a spaced apart manner over a substrate. The gate structure surrounds the first and second channel layers. The source/drain epitaxial structure is connected to the first and second channel layers. The source/drain contact is connected to the source/drain epitaxial structure. The second channel layer is closer to the source/drain contact than the first channel layer is to the source/drain contact, and the first channel layer is thicker than the second channel layer.

Abstract: A semiconductor device includes at least one fin, a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed on the at least one fin. The second dielectric layer between the at least one fin and the first dielectric layer. A thickness of the first dielectric layer on a sidewall of the at least one fin is less than a thickness of the second dielectric layer on the sidewall of the at least one fin.

Abstract: An epitaxial structure includes a first type semiconductor layer, a light emitting layer, a second type semiconductor layer, and a buffer layer structure. The light emitting layer is disposed on the first type semiconductor layer. The second type semiconductor layer is disposed on the light emitting layer. The buffer layer structure is disposed on one side of the first type semiconductor layer away from the second type semiconductor layer and includes a first buffer layer and a second buffer layer. The second buffer layer is located between the first buffer layer and the first type semiconductor layer, and the first buffer layer has a chlorine concentration greater than a chlorine concentration of the second buffer layer.

Abstract: An epitaxial semiconductor structure including a substrate, a semiconductor layer, and a balance structure is provided. The substrate has a first surface and a second surface opposite to each other. The semiconductor layer is formed on the first surface. The balance structure is formed on the second surface, the balance structure is configured to balance the thermal stress on the substrate, and the balance structure is composed of a plurality of non-continuous particulate materials. An epitaxial substrate is also provided.

Abstract: A heating apparatus including a rotating stage, a plurality of wafer carriers, a plurality of first heaters, and at least one second heater is provided. The plurality of wafer carriers is disposed on the rotating stage. The rotating stage drives the wafer carriers to rotate around a rotating axis of the rotating stage. The plurality of first heaters is disposed under a first heating region, each have a first width Wa. There is a first spacing Sa between any two adjacent first heaters. The at least one second heater is disposed under a second heating region, and has a second width Wb. There is a smallest spacing Sab between the at least one second heater and the first heating region, and Wa, Wb, Sa and Sab satisfy the equation: Wa/(Wa+Sa) ? Wb/(Wb+Sab). Each wafer carrier overlaps the first heating region in the axial direction of the rotating axis.

Abstract: A micro light-emitting diode includes a first stacked layer, a second stacked layer, a third stacked layer, a bonding layer, at least one etch stop layer, and a plurality of electrodes. The second stacked layer is disposed between the first stacked layer and the third stacked layer. The first stacked layer includes a first active layer. The second stacked layer includes a second active layer. The third stacked layer includes a third active layer. The bonding layer is disposed between the second stacked layer and the third stacked layer. The at least one etch stop layer is at least disposed between the first active layer and the second active layer. The plurality of electrodes are respectively electrically connected with the first stacked layer, the second stacked layer, and the third stacked layer. At least one electrode of the plurality of electrodes contacts the etch stop layer.

Abstract: Herein disclosed are a wafer, a wafer testing system, and a method thereof. Said wafer testing method comprises the following steps. First, an incident light is provided toward a wafer. And, a wafer surface image corresponded to the wafer is generated. Then, determining whether the wafer surface image has a plurality of first strips and a plurality of second strips, and the plurality of first strips and the plurality of second strips are symmetrical. When the wafer surface image has the plurality of first strips and the plurality of second strips, and the plurality of first strips and the plurality of second strips are symmetrical, a qualified signal corresponded to the wafer is provided.

Abstract: A heating apparatus including a rotating stage, a plurality of wafer carriers, a first heater, and a second heater is provided. The rotating stage includes a rotating axis. The plurality of wafer carriers is disposed on the rotating stage. The rotating stage drives the wafer carriers to rotate on the rotating axis. The first heater is disposed under the rotating stage. The first heater includes a first width in a radial direction of the rotating stage. The second heater is disposed under the rotating stage. The second heater and the first heater are separated from each other. The second heater includes a second width in the radial direction of the rotating stage, and the first width is not equal to the second width. A chemical vapor deposition (CVD) system using the heating apparatus is also provided.

Abstract: An epitaxial semiconductor structure including a substrate, a semiconductor layer, and a balance structure is provided. The substrate has a first surface and a second surface opposite to each other. The semiconductor layer is formed on the first surface. The balance structure is formed on the second surface, the balance structure is configured to balance the thermal stress on the substrate, and the balance structure is composed of a plurality of non-continuous particulate materials. An epitaxial substrate is also provided.

Abstract: A semiconductor wafer carrier structure includes a carrier body having a surface; a protective film covering the surface; a susceptor disposed on the carrier body; and a patterned coating film on the susceptor, wherein the patterned coating film has two or more different thicknesses, wherein patterns of the patterned coating film are symmetrically distributed with respect to a center of the susceptor.

Abstract: A semiconductor wafer carrier structure is provided. The semiconductor wafer carrier structure includes a susceptor and a patterned heat conduction part disposed on the susceptor. At least a portion of the patterned heat conduction part has a different heat conduction coefficient than the susceptor. A metal-organic chemical vapor deposition equipment is also provided. The metal-organic chemical vapor deposition equipment includes a carrier body having a plurality of carrier units. The above semiconductor wafer carrier structure is placed in at least one of the carrier units.

Abstract: A tray structure adapted to a deposition apparatus is provided. The tray structure includes a first tray and a second tray, wherein the first tray is disposed on the deposition apparatus for control of temperature and includes a first carrying portion and at least one heat-conducting structure. The first carrying portion is disposed on a top surface of the first tray. The at least one heat-conducting structure is disposed in a recess of the first carrying portion. The second tray is disposed on the first carrying portion and the at least one heat-conducting structure.

Abstract: Herein disclosed are a wafer, a wafer testing system, and a method thereof. Said wafer testing method comprises the following steps. First, an incident light is provided toward a wafer. And, a wafer surface image corresponded to the wafer is generated. Then, determining whether the wafer surface image has a plurality of first strips and a plurality of second strips, and the plurality of first strips and the plurality of second strips are symmetrical.

Abstract: A heating apparatus including a rotating stage, a plurality of wafer carriers, a plurality of first heaters, and at least one second heater is provided. The rotating stage includes a rotating axis. The plurality of wafer carriers is disposed on the rotating stage. The rotating stage drives the wafer carriers to rotate by taking the rotating axis as a center. The plurality of first heaters is disposed under a first heating region of the rotating stage. There is a first spacing between any two adjacent first heaters. The at least one second heater is disposed under a second heating region of the rotating stage. There is a spacing between the second heating region and the first heating region, and the spacing is not equal to the first spacing. A chemical vapor deposition (CVD) system using the heating apparatus is also provided.

Abstract: A heating apparatus including a rotating stage, a plurality of wafer carriers, a first heater, and a second heater is provided. The rotating stage includes a rotating axis. The plurality of wafer carriers is disposed on the rotating stage. The rotating stage drives the wafer carriers to rotate on the rotating axis. The first heater is disposed under the rotating stage. The first heater includes a first width in a radial direction of the rotating stage. The second heater is disposed under the rotating stage. The second heater and the first heater are separated from each other. The second heater includes a second width in the radial direction of the rotating stage, and the first width is not equal to the second width. A chemical vapor deposition (CVD) system using the heating apparatus is also provided.

Abstract: Calibration of models for manufacturing processes that are subject to circuit layout proximity effects is performed, including optical proximity correction (OPC) model calibration. A target structure is produced using a layout and a manufacturing process. The target structure is illuminated and an electromagnetic scattering property is detected. A manufacturing process model for simulation of the manufacturing process is produced, which comprises at least one manufacturing process parameter determining a model electromagnetic scattering property using the manufacturing process model and the layout. The model electromagnetic scattering property is compared to the detected electromagnetic scattering property and based on the result of the comparison, calibrated manufacturing process parameters are output for calibrating the manufacturing process model.

Abstract: In a multiple patterning techniques, where two or more exposures are used to form a single layer of a device, the splitting of features in a single layer between the multiple exposures is carried out additionally with reference to features of another associated layer and the splitting of that layer into two or more sets of features for separate exposure. The multiple exposure process can be a process involving repeated litho-etch steps desirably, the alignment scheme utilized during exposure of the split layers is optimized with reference to the splitting approach.

Abstract: In a multiple patterning techniques, where two or more exposures are used to form a single layer of a device, the splitting of features in a single layer between the multiple exposures is carried out additionally with reference to features of another associated layer and the splitting of that layer into two or more sets of features for separate exposure. The multiple exposure process can be a process involving repeated litho-etch steps desirably, the alignment scheme utilized during exposure of the split layers is optimized with reference to the splitting approach.