Patents by Inventor Chi-Heng Huang

Chi-Heng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integration scheme for breakdown voltage enhancement of a piezoelectric metal-insulator-metal device
    Patent number: 11984261
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
  • SEMICONDUCTOR DEVICE
    Publication number: 20240145412
    Abstract: A semiconductor device includes a logic circuit region having at least one core device and at least one input/output (I/O) device. The at least one core device has a first accumulative antenna ratio, and the at least one I/O device has a second accumulative antenna ratio. The first accumulative antenna ratio is greater than the second accumulative antenna ratio.
    Type: Application
    Filed: November 27, 2022
    Publication date: May 2, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Che Huang, Chao-Ting Chen, Jui-Fa Lu, Chi-Heng Lin
  • Advisory system for verifying sensitive circuits in chip-design
    Patent number: 8418098
    Abstract: A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: April 9, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Heng Huang, Gary Lin, Chu-Fu Chen, Yi-Kan Cheng, Fu-Lung Hsueh
  • Advisory System for Verifying Sensitive Circuits in Chip-Design
    Publication number: 20090172617
    Abstract: A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits.
    Type: Application
    Filed: March 24, 2008
    Publication date: July 2, 2009
    Inventors: Chi-Heng Huang, Gary Lin, Chu-Fu Chen, Yi-Kan Cheng, Fu-Lung Hsueh