Abstract: A display device is provided. The display device includes a display panel including a plurality of pixel arrangement areas, a data driving unit including a plurality of source drivers, and a timing controller configured to process data that is input from an external device and configured to generate output data. Each of the plurality of pixel arrangement areas includes a plurality of pixels arranged in areas in which a plurality of gate lines intersect a plurality of data lines. Each of the plurality of source drivers outputs display data to data lines of its corresponding pixels. The timing controller classifies the plurality of pixel arrangement areas based on a distance between the timing controller and each of the plurality of pixel arrangement areas, and transmits the output data to the data driving unit at at least two transmission speeds based on the classification.

Abstract: A display device is provided. The display device includes a display panel including a plurality of pixel arrangement areas, a data driving unit including a plurality of source drivers, and a timing controller configured to process data that is input from an external device and configured to generate output data. Each of the plurality of pixel arrangement areas includes a plurality of pixels arranged in areas in which a plurality of gate lines intersect a plurality of data lines. Each of the plurality of source drivers outputs display data to data lines of its corresponding pixels. The timing controller classifies the plurality of pixel arrangement areas based on a distance between the timing controller and each of the plurality of pixel arrangement areas, and transmits the output data to the data driving unit at at least two transmission speeds based on the classification.

Abstract: A method and a device for generating a clock signal determine a number of pulses to be discarded from each predetermined cycle of a reference clock signal in order to obtain, on average, a target frequency. A masking pattern is created for discarding the number of pulses to be discarded from each predetermined cycle of the reference clock signal. The clock signal, which includes the target frequency, is generated by discarding the number of pulses from the reference clock signal using the masking pattern.

Abstract: An emulation system includes a first circuit for emulating a first logical part of a device, a second circuit for emulating a second logical part of the device that is different from the first logical part, wherein the first circuit is separate from the second circuit, and a third circuit connecting the first circuit and the second circuit to communicate signals between the first circuit and the second circuit.

Abstract: An emulation system includes a controller, an emulation calculator, an emulation storage unit, and an interface unit. The emulation calculator includes a device under test (DUT) and emulates the DUT. The emulation storage unit stores emulation data of the DUT emulated by the emulation calculator under the control of the controller. The interface unit distributes and transfers the emulation data to a plurality of computers under the control of the controller.

Abstract: A method and a device for generating a clock signal determine a number of pulses to be discarded from each predetermined cycle of a reference clock signal in order to obtain, on average, a target frequency. A masking pattern is created for discarding the number of pulses to be discarded from each predetermined cycle of the reference clock signal. The clock signal, which includes the target frequency, is generated by discarding the number of pulses from the reference clock signal using the masking pattern.

Abstract: A method and system for distributed simultaneous simulation are provided, the method including providing a state of at least one storage unit, providing a segment of the circuit bounded by the at least one storage unit, and simulating the segment in accordance with the state of the at least one storage unit; and the system including a memory for describing storage units of a circuit, maintaining states of the storage units, and identifying distributed segments comprising combinational logic separated by the storage units, and processing units, each for simultaneously simulating at least one of the segments in accordance with the maintained states.

Abstract: A circuit emulation system and method are provided, the system including at least one trace chain and a trace memory in signal communication with the at least one trace chain for sequentially receiving values and feeding them back through the chain to their original storage unit positions; and the method including modeling the circuit, providing at least one storage unit in the model, emulating the circuit with the model, extracting a state of the at least one storage unit during emulation, storing the extracted state, and restoring the stored state through a feedback loop.

Abstract: An emulation system includes a first circuit for emulating a first logical part of a device, a second circuit for emulating a second logical part of the device that is different from the first logical part, wherein the first circuit is separate from the second circuit, and a third circuit connecting the first circuit and the second circuit to communicate signals between the first circuit and the second circuit.

Abstract: A method and a device for generating a clock signal determine a number of pulses to be discarded from each predetermined cycle of a reference clock signal in order to obtain, on average, a target frequency. A masking pattern is created for discarding the number of pulses to be discarded from each predetermined cycle of the reference clock signal. The clock signal, which includes the target frequency, is generated by discarding the number of pulses from the reference clock signal using the masking pattern.

Abstract: An emulation system includes a controller, an emulation calculator, an emulation storage unit, and an interface unit. The emulation calculator includes a device under test (DUT) and emulates the DUT. The emulation storage unit stores emulation data of the DUT emulated by the emulation calculator under the control of the controller. The interface unit distributes and transfers the emulation data to a plurality of computers under the control of the controller.

Abstract: A circuit emulation system and method are provided, the system including at least one trace chain and a trace memory in signal communication with the at least one trace chain for sequentially receiving values and feeding them back through the chain to their original storage unit positions; and the method including modeling the circuit, providing at least one storage unit in the model, emulating the circuit with the model, extracting a state of the at least one storage unit during emulation, storing the extracted state, and restoring the stored state through a feedback loop.

Abstract: A method and system for distributed simultaneous simulation are provided, the method including providing a state of at least one storage unit, providing a segment of the circuit bounded by the at least one storage unit, and simulating the segment in accordance with the state of the at least one storage unit; and the system including a memory for describing storage units of a circuit, maintaining states of the storage units, and identifying distributed segments comprising combinational logic separated by the storage units, and processing units, each for simultaneously simulating at least one of the segments in accordance with the maintained states.

Abstract: An Orthogonal Frequency Division Multiplexing (OFDM) receiver of a wireless Local Area Network (LAN) system uses double cross-correlation and double peak-value comparison for symbol timing synchronization. The OFDM receiver of the wireless LAN system performs first differential cross-correlation using a short training symbol as a reference signal, performs second differential cross-correlation for an output value of the first differential cross-correlation, and performs double peak-value comparison for an output value of the second differential cross-correlation. In this way, fast symbol synchronization is achieved due to an excellent correlation property. Accordingly, a wireless LAN system including the OFDM receiver has a high response speed.

Abstract: An Orthogonal Frequency Division Multiplexing (OFDM) receiver of a wireless Local Area Network (LAN) system uses double cross-correlation and double peak-value comparison for symbol timing synchronization. The OFDM receiver of the wireless LAN system performs first differential cross-correlation using a short training symbol as a reference signal, performs second differential cross-correlation for an output value of the first differential cross-correlation, and performs double peak-value comparison for an output value of the second differential cross-correlation. In this way, fast symbol synchronization is achieved due to an excellent correlation property. Accordingly, a wireless LAN system including the OFDM receiver has a high response speed.