Patents by Inventor Chi Hoo Wan

Chi Hoo Wan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Packaged semiconductor device with interior polygonal pads
    Patent number: 10056343
    Abstract: Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure defining a rectangular boundary and having a bottom surface that includes interior polygonal pads exposed at the bottom surface of the package structure and located on a centerline of the bottom surface of the package structure and edge polygonal pads exposed at the bottom surface of the package structure, located at an edge of the rectangular boundary, and including one edge polygonal pad in the vicinity of each corner of the rectangular boundary. The interior polygonal pads are configured such that a line running between at least one vertex of each of the interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: August 21, 2018
    Assignee: Nexperia B.V.
    Inventors: Roelf A. J. Groenhuis, Kan Wae Lam, Clifford J. Lloyd, Chi Hoo Wan, Fei Ying Wong
  • PACKAGED SEMICONDUCTOR DEVICE WITH INTERIOR POLYGONAL PADS
    Publication number: 20160118357
    Abstract: Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure defining a rectangular boundary and having a bottom surface that includes interior polygonal pads exposed at the bottom surface of the package structure and located on a centerline of the bottom surface of the package structure and edge polygonal pads exposed at the bottom surface of the package structure, located at an edge of the rectangular boundary, and including one edge polygonal pad in the vicinity of each corner of the rectangular boundary. The interior polygonal pads are configured such that a line running between at least one vertex of each of the interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure.
    Type: Application
    Filed: January 7, 2016
    Publication date: April 28, 2016
    Applicant: NXP B.V.
    Inventors: Roelf A.J. Groenhuis, Kan Wae Lam, Clifford J. Lloyd, Chi Hoo Wan, Fei Ying Wong
  • Packaged semiconductor device with interior polygonal pads
    Patent number: 9269690
    Abstract: Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure defining a rectangular boundary and having a bottom surface that includes interior polygonal pads exposed at the bottom surface of the package structure and located on a centerline of the bottom surface of the package structure and edge polygonal pads exposed at the bottom surface of the package structure, located at an edge of the rectangular boundary, and including one edge polygonal pad in the vicinity of each corner of the rectangular boundary. The interior polygonal pads are configured such that a line running between at least one vertex of each of the interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: February 23, 2016
    Assignee: NXP B.V.
    Inventors: Roelf A. J. Groenhuis, Kan Wae Lam, Clifford J. Lloyd, Chi Hoo Wan, Fei Ying Wong
  • PACKAGED SEMICONDUCTOR DEVICE WITH INTERIOR POLYGONAL PADS
    Publication number: 20150162298
    Abstract: Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure defining a rectangular boundary and having a bottom surface that includes interior polygonal pads exposed at the bottom surface of the package structure and located on a centerline of the bottom surface of the package structure and edge polygonal pads exposed at the bottom surface of the package structure, located at an edge of the rectangular boundary, and including one edge polygonal pad in the vicinity of each corner of the rectangular boundary. The interior polygonal pads are configured such that a line running between at least one vertex of each of the interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure.
    Type: Application
    Filed: December 6, 2013
    Publication date: June 11, 2015
    Applicant: NXP B.V.
    Inventors: Roelf A.J. Groenhuis, Kan Wae Lam, Clifford J. Lloyd, Chi Hoo Wan, Fei Ying Wong