Patents by Inventor Chi-hsiang Chin

Chi-hsiang Chin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Seamless bit-level low-latency retimer for data links
    Patent number: 11159353
    Abstract: This application is directed to transferring data over a data link coupled between two electronic devices. The data link includes a retimer having a full data path and a bit level data path that are coupled in parallel. A first sequence of data packets is transferred via the bit level data path of the retimer. While transferring the first sequence of data packets, the data link detects initiation of an equalization procedure based on an initiation data packet in the first sequence of data packets. In accordance with detection of the initiation of the equalization procedure, the data link selects the full data path of the retimer for data transfer over the data link. During the equalization procedure, a second sequence of data packets immediately follows the first sequence of data packets, and is transferred via the full data path of the retimer.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: October 26, 2021
    Assignee: PARADE TECHNOLOGIES, LTD.
    Inventors: Xiang Chen, Ming Qu, Chi-hsiang Chin, Haijun Zhu
  • Seamless bit-level low-latency retimer for data links
    Patent number: 10979258
    Abstract: This application is directed to transferring data over a data link coupled between two electronic devices. The data link includes a retimer having a full data path and a bit level data path that are coupled in parallel. A first sequence of data packets is transferred via the bit level data path of the retimer. While transferring the first sequence of data packets, the data link detects initiation of an equalization procedure based on an initiation data packet in the first sequence of data packets. In accordance with detection of the initiation of the equalization procedure, the data link selects the full data path of the retimer for data transfer over the data link. During the equalization procedure, a second sequence of data packets immediately follows the first sequence of data packets, and is transferred via the full data path of the retimer.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: April 13, 2021
    Assignee: PARADE TECHNOLOGIES, LTD.
    Inventors: Xiang Chen, Ming Qu, Chi-hsiang Chin, Haijun Zhu