Abstract: A memory cell array includes a first and a second column of memory cells, a first and a second bit line, a source line and a first set of vias. The first or second bit line includes a first conductive line located on a first metal layer, and a second conductive line located on a second metal layer. The first and second conductive lines overlap a source of a transistor of a memory cell of the first column or second column of memory cells. The source line is coupled to the first and second column of memory cells. The first set of vias is electrically coupled to the first and second conductive line. A pair of vias of the first set of vias is located above where the first conductive line overlaps each memory cell of the first or second column of memory cells.

Abstract: A memory cell array includes a first and a second column of memory cells, a first and a second bit line, a source line and a first set of vias. The second bit line includes a first conductive line located on a first metal layer, and a second conductive line located on a second metal layer. The first and second conductive lines overlap a source of a transistor of a memory cell of the second column of memory cells. The source line is coupled to the first and second column of memory cells. The first set of vias is electrically coupled to the first and second conductive line. A pair of vias of the first set of vias is located above where the first conductive line overlaps each memory cell of the second column of memory cells.

Abstract: A memory cell array includes a first and a second column of memory cells, a first and a second bit line, a source line and a first set of vias. The first or second bit line includes a first conductive line located on a first metal layer, and a second conductive line located on a second metal layer. The first and second conductive lines overlap a source of a transistor of a memory cell of the first column or second column of memory cells. The source line is coupled to the first and second column of memory cells. The first set of vias is electrically coupled to the first and second conductive line. A pair of vias of the first set of vias is located above where the first conductive line overlaps each memory cell of the first or second column of memory cells.

Abstract: A memory cell array includes a first column of memory cells, a second column of memory cells, a first bit line, a second bit line and a source line. The second column of memory cells is separated from the first column of memory cells in a first direction. The first column of memory cells and the second column of memory cells are arranged in a second direction. The first bit line is coupled to the first column of memory cells, and extends in the second direction. The second bit line is coupled to the second column of memory cells, and extends in the second direction. The source line extends in the second direction, is coupled to the first column of memory cells and the second column of memory cells.

Abstract: A memory cell array includes a first column of memory cells, a second column of memory cells, a first bit line, a second bit line and a source line. The second column of memory cells is separated from the first column of memory cells in a first direction. The first column of memory cells and the second column of memory cells are arranged in a second direction. The first bit line is coupled to the first column of memory cells, and extends in the second direction. The second bit line is coupled to the second column of memory cells, and extends in the second direction. The source line extends in the second direction, is coupled to the first column of memory cells and the second column of memory cells.

Abstract: The disclosure provides a method and system for detecting an anaerobic threshold heart rate. After first physiological data, second physiological data and third physiological data are obtained while a user is exercising, an interval of the third physiological data corresponding to an estimated range of first physiological data and a turning point of a curve fitting the third physiological data within the interval are obtained, to determine the anaerobic threshold heart rate of a user.

Abstract: A method for controlling an electronic equipment and a wearable device are provided, respectively. The method for controlling the electronic equipment includes the following steps. An inertial signal is detected. A gesture is obtained by dividing the inertial signal or classifying the inertial signal. A controlling command is outputted based on the gesture to control the electronic equipment, such as a desktop device, a portable device or the wearable device.

Abstract: A method for controlling an electronic equipment and a wearable device are provided, respectively. The method for controlling the electronic equipment includes the following steps. An inertial signal is detected. A gesture is obtained by dividing the inertial signal or classifying the inertial signal. A controlling command is outputted based on the gesture to control the electronic equipment, such as a desktop device, a portable device or the wearable device.

Abstract: The disclosure provides a method and system for detecting an anaerobic threshold heart rate. After first physiological data, second physiological data and third physiological data are obtained while a user is exercising, an interval of the third physiological data corresponding to an estimated range of first physiological data and a turning point of a curve fitting the third physiological data within the interval are obtained, to determine the anaerobic threshold heart rate of a user.

Abstract: Among other things, techniques and systems are provided to pre-charge a node of a primary circuit, such as a voltage regulator or bandgap voltage reference, via a start-up circuit. The node is charged to a specified voltage during a pre-charge operation that occurs while the primary-circuit is powered-off. The pre-charge operation comprises discharging a voltage from the node during a first portion of the pre-charge operation and re-charging the node to the specified voltage during a second portion of the pre-charge operation. In some embodiments, the specified voltage is substantially equivalent to a switching voltage of a drive transistor of the primary circuit.

Abstract: Among other things, techniques and systems are provided to pre-charge a node of a primary circuit, such as a voltage regulator or bandgap voltage reference, via a start-up circuit. The node is charged to a specified voltage during a pre-charge operation that occurs while the primary-circuit is powered-off. The pre-charge operation comprises discharging a voltage from the node during a first portion of the pre-charge operation and re-charging the node to the specified voltage during a second portion of the pre-charge operation. In some embodiments, the specified voltage is substantially equivalent to a switching voltage of a drive transistor of the primary circuit.