Abstract: A high electron mobility transistor includes a substrate. A channel layer is disposed on the substrate. An active layer is disposed on the channel layer. The active layer includes a P-type aluminum gallium nitride layer. A P-type gallium nitride gate is disposed on the active layer. A source electrode and a drain electrode are disposed on the active layer.

Abstract: A metal processing and forming system and a metal processing and forming method for forming a workpiece on a workbench are provided. The system includes a forming device, a shaping device, and a control device. The forming device is configured for providing a metallic material according to a processing path and forming an initial melt of the metallic material. The shaping device is configured for shaping the initial melt. The control device is coupled to the forming device and the shaping device and configured for synchronously controlling the forming device and the shaping device. The control device controls the shaping device to shape the initial melt, before the initial melt is solidified, to form the workpiece.

Abstract: A high electron mobility transistor includes a substrate. A channel layer is disposed on the substrate. An active layer is disposed on the channel layer. The active layer includes a P-type aluminum gallium nitride layer. A P-type gallium nitride gate is disposed on the active layer. A source electrode and a drain electrode are disposed on the active layer.

Abstract: A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.

Abstract: An electronic device and a method for predicting a blockage of a coronary artery are provided. The method includes: obtaining multiple pieces of electrocardiogram (ECG) data respectively corresponding to a coronary artery set; generating multiple first probabilities corresponding to the multiple pieces of electrocardiogram data respectively according to the multiple pieces of electrocardiogram data and a first phase model, generating a first determined result according to the multiple first probabilities, and selecting a first data subset corresponding to a first probability subset from the multiple pieces of electrocardiogram data in response to each one in the first data subset of the multiple first probabilities being greater than a first threshold; generating multiple second probabilities corresponding to the first data subset according to the first data subset and a second phase model, and generating a second determined result according to the multiple second probabilities.

Abstract: An electronic device and a method for selecting a feature of an electrocardiogram (ECG) are provided. The method includes: obtaining the ECG; performing a first pre-processing on the ECG to generate a first ECG; marking multiple extreme points corresponding to at least one type of wave on the first ECG; calculating a first feature value corresponding to a first feature according to the multiple extreme points of the at least one type of wave, generating a first performance index corresponding to a machine learning model according to the first feature value, and determining whether to select the first feature according to the first performance index; and outputting the first feature in response to selecting the first feature.

Abstract: A high electron mobility transistor (HEMT) device including the following components is provided. A gate electrode is located on a barrier layer. A source electrode is located on the first side of the gate electrode. A drain electrode is located on the second side of the gate. A source field plate is connected to the source electrode. The source field plate includes first, second, and third field plate portions. The first field plate portion is connected to the source electrode and is located on the first side of the gate electrode. The second field plate portion is located on the second side of the gate electrode. The third field plate portion is connected to the end of the first field plate portion and the end of the second field plate portion. The source field plate has a first opening located directly above the gate electrode.

Abstract: A method for establishing a disease prediction model is provided. The method includes the steps of extracting feature values for multiple microbiota features from microbiota data of each of a plurality of samples, selecting a portion of the extracted microbiota features as selected features, and training a disease prediction model. Each piece of training data used in training the disease prediction model includes (i) disease data for each of the samples and (ii) the feature values of the selected features for the sample. The microbiota features include species-level features, microbiota interaction features, and community-level features.

Abstract: A pixel detection device includes a substrate. Substrate includes a sub-pixel circuit, a detection transistor, and two second detection boards. Sub-pixel circuit includes a light emitting element. First detection board is coupled to detection transistor. Second detection board is coupled to light emitting element. First detection board outputs a first detecting signal in a sub-stage of a stage, and first detecting signal is switched from a first voltage level to a second voltage level to control a first voltage of detection transistor. Second detection board outputs a second detecting signal at sub-stage, and second detecting signal is switched from second voltage level to first voltage level to control a second voltage of first light emitting element. Detection transistor and light emitting element are conducted according to first voltage and second voltage to light up light emitting element, so as to detect whether brightness of light emitting element is abnormal.

Abstract: Some embodiments relate to an IC device, including a first chip comprising a plurality of pixel blocks respectively including one of a first plurality of conductive pads, the plurality of pixel blocks arranged in rows extending in a first direction and columns extending in a second direction perpendicular to the first direction; a second chip bonded to the first chip at a bonding interface, where the second chip comprises a second plurality of conductive pad recessed and contacting the first plurality of conductive pads along the bonding interface; and a first corrugated shield line having outermost edges set-back along the second direction from outermost edges of a first row of the plurality of pixel blocks, the first corrugated shield line being arranged within a first dielectric layer and laterally separating neighboring ones of the first plurality of conductive pads within the first row of the plurality of pixel blocks.

Abstract: The present disclosure relates to an image sensor integrated chip structure. The image sensor integrated chip structure includes one or more logic devices disposed within a first substrate and coupled to a first interconnect structure on the first substrate. A plurality of pixel support devices are disposed along a first-side of a second substrate and coupled to a second interconnect structure on the second substrate. The first substrate is bonded to the second substrate. A plurality of image sensing elements are disposed within a third substrate in pixel regions respectively including two or more of the plurality of image sensing elements. A plurality of transfer gates and a third interconnect structure are disposed on a first-side of the third substrate. The third interconnect structure includes interconnect wires and vias confined between the first-side of second substrate and the first-side of the third substrate.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor comprising a pixel with a dual-PD layout for enhanced scaling down. The pixel spans a first integrated circuit (IC) die and a second IC die stacked with the first IC die. The pixel comprises a plurality of photodetectors in the first IC die, and further comprises a plurality of pixel transistors split amongst the first IC die and the second IC die. The plurality of photodetectors are grouped into one or more pairs, each having the dual-PD layout. A DTI structure completely and individually surrounds the plurality of photodetectors, and further extends completely through a substrate within which the plurality of photodetectors are arranged. As such, the DTI structure completely separates the plurality of photodetectors from each other.

Abstract: A self-driven power generation module and a manufacturing method thereof are provided. The self-driven power generation module includes an upper structure, a lower structure, and a charge accumulation layer. The upper structure includes a first encapsulating layer, a first supporting layer, and a first electrode layer. The first supporting layer contacts the first encapsulating layer. The first electrode layer contacts the first supporting layer. The lower structure is spaced apart from the upper structure. The lower structure includes a second encapsulating layer, a second supporting layer, a second electrode layer, a third supporting layer, and a third electrode layer. The third supporting layer is disposed on the second encapsulating layer and spaced apart from the second supporting layer. The third electrode layer is disposed on the third supporting layer. The charge accumulation layer is disposed between the upper structure and the lower structure.

Abstract: An integrated chip including a first semiconductor substrate. The first semiconductor substrate includes a doped region. A first photodetector and a second photodetector are in the first semiconductor substrate. A trench isolation layer at least partially surrounds the first photodetector and the second photodetector and extends between the first photodetector and the second photodetector. The trench isolation layer has a first pair of sidewalls. The first semiconductor substrate extends from the first photodetector, between the first pair of sidewalls, to the second photodetector. The doped region is between the first pair of sidewalls. The first photodetector and a first gate partially form a first transistor. The second photodetector and a second gate partially form a second transistor. A second semiconductor substrate is over the first gate and the second gate. A third transistor is along the second semiconductor substrate. The third transistor is coupled to the first transistor.

Abstract: Methods for producing single crystal silicon wafers for use in insulated gate bipolar transistors are disclosed. The methods may involve determining the radial profile of a ratio between (i) a growth velocity, v, and (ii) an axial temperature gradient, G for an ingot with relatively low oxygen. Based on the radial v/G profile, a nitrogen concentration which widens the v/G window to produce Perfect Silicon free of COP and gate oxide failures may be selected.

Abstract: A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.

Abstract: The present invention relates to 9-oxo-9,10-dihydro-6H-pyrano[3,2-b:4,5-b?]dipyridine-8-carboxylic acid derivatives, their manufacture, pharmaceutical compositions containing them and their use as a medicament.

Abstract: A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.

Abstract: A flexible tube includes a first connecting portion and a second connecting section. The second connecting section and the first connecting section are integrally connected to each other. The first connecting section has a first end surface, and the second connecting section has a second end surface, wherein there is an acute angle between the first end surface and the second end surface.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a gate structure disposed on the substrate. The semiconductor device also includes a source region and a drain region disposed within the substrate. The substrate includes a drift region laterally extending between the source region and the drain region. The semiconductor device further includes a first stressor layer disposed over the drift region of the substrate. The first stressor layer is configured to apply a first stress to the drift region of the substrate. In addition, the semiconductor device includes a second stressor layer disposed on the first stressor layer. The second stressor layer is configured to apply a second stress to the drift region of the substrate, and the first stress is opposite to the second stress.