Patents by Inventor Chi-hsin Chang

Chi-hsin Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10990505
    Abstract: A method for composing a scene using a data module includes: receiving, from a user, an instruction to instantiate the data module to produce at least a first instance of the data module in a second data module; receiving, from the user, a first override for modifying the first instance of the data module; receiving, from the user, a second override for modifying the data module; identifying a conflict introduced by the first override or the second override; configuring a display interface to display an indication informing the user of the identified conflict; configuring the display interface to display one or more options for resolving the identified conflict; receiving, from the user, a selection of an option of the one or more options; and in response to the selection of the option, resolving the identified conflict by deleting the first override or the second override.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: April 27, 2021
    Assignee: DREAMWORKS ANIMATION LLC
    Inventors: Esteban Papp, Chi-Wei Tseng, Stuart Bryson, Matthew Christopher Gong, Yu-Hsin Chang
  • Publication number: 20200273754
    Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
  • Patent number: 10692769
    Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
  • Patent number: 10651090
    Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
  • Publication number: 20190189614
    Abstract: A method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 20, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Juei LEE, Chia-Ming LIANG, Chi-Hsin CHANG, Jin-Aun NG, Yi-Shien MOR, Huai-Hsien CHIU
  • Publication number: 20190067112
    Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.
    Type: Application
    Filed: October 31, 2017
    Publication date: February 28, 2019
    Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
  • Patent number: 10204905
    Abstract: A semiconductor structure includes a substrate, a first gate structure, and a second gate structure. The substrate has a plurality of first fins and a plurality of second fins, wherein a first pitch between two adjacent first fins is greater than a second pitch between two adjacent second fins. The first gate structure crosses over the first fins. The second gate structure crosses over the second fins, wherein the second gate structure includes an upper portion having two first sidewalls substantially parallel to each other and a lower portion tapers toward the substrate.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Juei Lee, Chia-Ming Liang, Chi-Hsin Chang, Jin-Aun Ng, Yi-Shien Mor, Huai-Hsien Chiu
  • Publication number: 20180308842
    Abstract: A semiconductor structure includes a substrate, a first gate structure, and a second gate structure. The substrate has a plurality of first fins and a plurality of second fins, wherein a first pitch between two adjacent first fins is greater than a second pitch between two adjacent second fins. The first gate structure crosses over the first fins. The second gate structure crosses over the second fins, wherein the second gate structure includes an upper portion having two first sidewalls substantially parallel to each other and a lower portion tapers toward the substrate.
    Type: Application
    Filed: June 23, 2017
    Publication date: October 25, 2018
    Inventors: Yi-Juei LEE, Chia-Ming LIANG, Chi-Hsin CHANG, Jin-Aun NG, Yi-Shien MOR, Huai-Hsien CHIU
  • Patent number: 8854897
    Abstract: A static random access memory apparatus and a bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: October 7, 2014
    Assignees: Faraday Technology Corp., National Chiao Tung University
    Inventors: Ching-Te Chuang, Nan-Chun Lien, Wei-Nan Liao, Chi-Hsin Chang, Hao-I Yang, Wei Hwang, Ming-Hsien Tu
  • Publication number: 20140009999
    Abstract: A static random access memory apparatus and a bit-line voltage controller thereof are disclosed. The bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.
    Type: Application
    Filed: November 1, 2012
    Publication date: January 9, 2014
    Inventors: Ching-Te Chuang, Nan-Chun Lien, Wei-Nan Liao, Chi-Hsin Chang, Hao-I Yang, Wei Hwang, Ming-Hsien Tu
  • Patent number: 8450161
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: May 28, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yu Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang
  • Publication number: 20120225529
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
    Type: Application
    Filed: May 7, 2012
    Publication date: September 6, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh-Hao Chen, Hao-Ming Lien, Ssu-Yu Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang
  • Patent number: 8193586
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: June 5, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yi Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang, Chien-Liang Chen
  • Publication number: 20100044803
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
    Type: Application
    Filed: February 20, 2009
    Publication date: February 25, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yi Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang
  • Patent number: 5638803
    Abstract: The present invention relates to a fueling control device for a remote-control model to prevent fuel oil overflow and to stop fueling automatically by sensing fuel oil delivery pressure. The device has a check valve, a pump and a control device with an electronic control consisting of a DC power supply circuit, a voltage regulation circuit, a switch type voltage regulation circuit, a control key, a CPU, a differential current inspection circuit, a motor circuit, and a motor driven pump. The check valve is connected between the fuel oil tank and an air conduit connected to a muffler. The pump is connected between a fuel oil drum, and a fuel oil delivery tube for pumping fuel oil from the fuel oil drum into the fuel oil tank. When the fuel oil tank is filled, overflow fuel oil causes closure of the check valve to cause a sudden rise of fuel oil delivery pressure. The rising load on the motor is transmitted to the control device to cause the pump to stop running.
    Type: Grant
    Filed: August 18, 1995
    Date of Patent: June 17, 1997
    Inventor: Chi-hsin Chang