Patents by Inventor Chi-Hsin Chiu
Chi-Hsin Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967546Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.Type: GrantFiled: July 21, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
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Publication number: 20240113188Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a first gate line, a second gate line, and a first auxiliary gate portion. The semiconductor substrate comprises a semiconductor fin. The semiconductor fin extends substantially along a first direction. The first gate line and the second gate line extend substantially along a second direction different form the first direction from a top view. The first auxiliary gate portion connects the first gate line to the second gate line from the top view.Type: ApplicationFiled: March 27, 2023Publication date: April 4, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Li CHIU, Yi-Juei LEE, Yu-Jie YE, Chi-Hsin CHANG, Chun-Jun LIN
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Publication number: 20230268328Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.Type: ApplicationFiled: April 28, 2023Publication date: August 24, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Kong-Toon Ng, Hung-Ho Lee, Chee-Key Chung, Chang-Fu LIN, Chi-Hsin Chiu
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Patent number: 11676948Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.Type: GrantFiled: June 3, 2021Date of Patent: June 13, 2023Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Kong-Toon Ng, Hung-Ho Lee, Chee-Key Chung, Chang-Fu Lin, Chi-Hsin Chiu
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Publication number: 20210296295Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.Type: ApplicationFiled: June 3, 2021Publication date: September 23, 2021Inventors: Kong-Toon Ng, Hung-Ho Lee, Chee-Key Chung, Chang-Fu Lin, Chi-Hsin Chiu
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Patent number: 11056470Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.Type: GrantFiled: July 16, 2019Date of Patent: July 6, 2021Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Kong-Toon Ng, Hung-Ho Lee, Chee-Key Chung, Chang-Fu Lin, Chi-Hsin Chiu
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Patent number: 10950507Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.Type: GrantFiled: May 7, 2018Date of Patent: March 16, 2021Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Lu-Yi Chen, Chi-Hsin Chiu, Shih-Kuang Chiu
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Publication number: 20200402965Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.Type: ApplicationFiled: July 16, 2019Publication date: December 24, 2020Inventors: Kong-Toon Ng, Hung-Ho Lee, Chee-Key Chung, Chang-Fu Lin, Chi-Hsin Chiu
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Patent number: 10615055Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.Type: GrantFiled: December 19, 2018Date of Patent: April 7, 2020Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chi-Hsin Chiu, Shih-Kuang Chiu
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Publication number: 20190122898Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.Type: ApplicationFiled: December 19, 2018Publication date: April 25, 2019Inventors: Chi-Hsin Chiu, Shih-Kuang Chiu
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Patent number: 10199239Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.Type: GrantFiled: August 11, 2015Date of Patent: February 5, 2019Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chi-Hsin Chiu, Shih-Kuang Chiu
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Publication number: 20180254227Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.Type: ApplicationFiled: May 7, 2018Publication date: September 6, 2018Inventors: Lu-Yi Chen, Chi-Hsin Chiu, Shih-Kuang Chiu
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Patent number: 9991178Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.Type: GrantFiled: September 14, 2012Date of Patent: June 5, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Lu-Yi Chen, Chi-Hsin Chiu, Shih-Kuang Chiu
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Publication number: 20170148761Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.Type: ApplicationFiled: January 6, 2017Publication date: May 25, 2017Inventors: Guang-Hwa Ma, Shih-Kuang Chiu, Shih-Ching Chen, Chun-Chi Ke, Chang-Lun Lu, Chun-Hung Lu, Hsien-Wen Chen, Chun-Tang Lin, Yi-Che Lai, Chi-Hsin Chiu, Wen-Tsung Tseng, Tsung-Te Yuan, Lu-Yi Chen, Mao-Hua Yeh
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Patent number: 9520304Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a semiconductor structure having a carrier, a circuit portion formed on the carrier and a plurality of semiconductor elements disposed on the circuit portion; disposing a lamination member on the semiconductor elements; forming an insulating layer on the circuit portion for encapsulating the semiconductor elements; and removing the carrier. The lamination member increases the strength between adjacent semiconductor elements so as to overcome the conventional cracking problem caused by a CTE mismatch between the semiconductor elements and the insulating layer when the carrier is removed.Type: GrantFiled: November 7, 2013Date of Patent: December 13, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Hong-Da Chang, Yi-Che Lai, Chi-Hsin Chiu, Shih-Kuang Chiu
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Publication number: 20160079136Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.Type: ApplicationFiled: August 11, 2015Publication date: March 17, 2016Inventors: Chi-Hsin Chiu, Shih-Kuang Chiu
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Patent number: 9254994Abstract: A package structure having at least an MEMS element is provided, including a chip having electrical connecting pads and the MEMS element; a lid disposed on the chip to cover the MEMS element and having a metal layer provided thereon; first sub-bonding wires electrically connecting to the electrical connecting pads; second sub-bonding wires electrically connecting to the metal layer; an encapsulant disposed on the chip, wherein the top ends of the first and second sub-bonding wires are exposed from the encapsulant; and metallic traces disposed on the encapsulant and electrically connecting to the first sub-bonding wires. The package structure advantageously features reduced size, relatively low costs, diverse bump locations, and an enhanced EMI shielding effect.Type: GrantFiled: September 16, 2014Date of Patent: February 9, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chi-Hsin Chiu, Chih-Ming Huang, Chang-Yueh Chan, Hsin-Yi Liao, Chun-Chi Ke
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Publication number: 20150102433Abstract: A package structure having at least an MEMS element is provided, including a chip having electrical connecting pads and the MEMS element; a lid disposed on the chip to cover the MEMS element and having a metal layer provided thereon; first sub-bonding wires electrically connecting to the electrical connecting pads; second sub-bonding wires electrically connecting to the metal layer; an encapsulant disposed on the chip, wherein the top ends of the first and second sub-bonding wires are exposed from the encapsulant; and metallic traces disposed on the encapsulant and electrically connecting to the first sub-bonding wires. The package structure advantageously features reduced size, relatively low costs, diverse bump locations, and an enhanced EMI shielding effect.Type: ApplicationFiled: September 16, 2014Publication date: April 16, 2015Inventors: Chi-Hsin Chiu, Chih-Ming Huang, Chang-Yueh Chan, Hsin-Yi Liao, Chun-Chi Ke
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Publication number: 20150041969Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a semiconductor structure having a carrier, a circuit portion formed on the carrier and a plurality of semiconductor elements disposed on the circuit portion; disposing a lamination member on the semiconductor elements; forming an insulating layer on the circuit portion for encapsulating the semiconductor elements; and removing the carrier. The lamination member increases the strength between adjacent semiconductor elements so as to overcome the conventional cracking problem caused by a CTE mismatch between the semiconductor elements and the insulating layer when the carrier is removed.Type: ApplicationFiled: November 7, 2013Publication date: February 12, 2015Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Hong-Da Chang, Yi-Che Lai, Chi-Hsin Chiu, Shih-Kuang Chiu
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Publication number: 20150035164Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.Type: ApplicationFiled: August 28, 2013Publication date: February 5, 2015Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Guang-Hwa Ma, Shih-Kuang Chiu, Shih-Ching Chen, Chun-Chi Ke, Chang-Lun Lu, Chun-Hung Lu, Hsien-Wen Chen, Chun-Tang Lin, Yi-Che Lai, Chi-Hsin Chiu, Wen-Tsung Tseng, Tsung-Te Yuan, Lu-Yi Chen, Mao-Hua Yeh