Patents by Inventor Chi-Hsiu Hsu

Chi-Hsiu Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12347486
    Abstract: A forming method of a ReRAM array includes steps as follows: Firstly, a first pulse is applied to a first ReRAM unit in the ReRAM array. Afterwards, a second pulse is applied to the first ReRAM unit, wherein the electrical property of the first pulse is opposite to that of the second pulse. Then, a verification pulse is applied to the first ReRAM unit to verify whether the first resistance value of the first ReRAM unit passes a preset threshold. When the first resistance value passes the preset threshold value, a third pulse is applied to the first ReRAM unit, wherein the first pulse and the third pulse have the same electrical property, and the first pulse has a voltage value substantially the same to that of the third pulse.
    Type: Grant
    Filed: May 24, 2023
    Date of Patent: July 1, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsiu Hsu, Yu-Huan Yeh, Cheng-Hsiao Lai, Guan-Lin Chen, Chuan-Fu Wang, Hung-Yu Fan Chiang
  • Patent number: 12237027
    Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.
    Type: Grant
    Filed: October 16, 2022
    Date of Patent: February 25, 2025
    Assignee: United Microelectronics Corp.
    Inventors: Chung-Hao Chen, Chi-Hsiu Hsu, Chi-Fa Lien, Ying-Ting Lin, Cheng-Hsiao Lai, Ya-Nan Mou
  • Publication number: 20240347108
    Abstract: A forming method of a ReRAM array includes steps as follows: Firstly, a first pulse is applied to a first ReRAM unit in the ReRAM array. Afterwards, a second pulse is applied to the first ReRAM unit, wherein the electrical property of the first pulse is opposite to that of the second pulse. Then, a verification pulse is applied to the first ReRAM unit to verify whether the first resistance value of the first ReRAM unit passes a preset threshold. When the first resistance value passes the preset threshold value, a third pulse is applied to the first ReRAM unit, wherein the first pulse and the third pulse have the same electrical property, and the first pulse has a voltage value substantially the same to that of the third pulse.
    Type: Application
    Filed: May 24, 2023
    Publication date: October 17, 2024
    Inventors: Chi-Hsiu HSU, Yu-Huan YEH, Cheng-Hsiao LAI, Guan-Lin CHEN, Chuan-Fu WANG, Hung-Yu FAN CHIANG
  • Publication number: 20240071535
    Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.
    Type: Application
    Filed: October 16, 2022
    Publication date: February 29, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Chung-Hao Chen, Chi-Hsiu Hsu, Chi-Fa Lien, Ying-Ting Lin, Cheng-Hsiao Lai, Ya-Nan Mou
  • Patent number: 10580499
    Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: March 3, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Pang Lu, Chi-Hsiu Hsu, Chung-Hao Chen, Ya-Nan Mou, Chung-Cheng Tsai
  • Publication number: 20190043587
    Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.
    Type: Application
    Filed: September 21, 2017
    Publication date: February 7, 2019
    Inventors: Hsin-Pang Lu, Chi-Hsiu Hsu, Chung-Hao Chen, Ya-Nan Mou, Chung-Cheng Tsai