Patents by Inventor Chi-Hsuan Cheng
Chi-Hsuan Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12206148Abstract: The invention discloses a filter device. The filter device comprises a substrate, at least one transmission conductor, and a reference conductor having a slotted structure. The substrate is provided at a first surface thereof with the transmission conductor, and provided at a second surface thereof with the reference conductor. The slotted structure comprises a frame portion, a slotted portion, and a hollow portion. The slotted portion surrounds the frame portion, and the hollow portion is formed in the frame portion. At least one impedance unit is configured on the frame portion. The equivalent filter circuit of the filter device is formed between the transmission conductor, the slotted structure, the reference conductor, and the impedance unit. Thereby, the equivalent filter circuit absorbs at least one noise at at least one specific frequency by the impedance unit to avoid the noise reflected to affect the transmission quality of signal.Type: GrantFiled: December 10, 2021Date of Patent: January 21, 2025Assignee: National Taiwan UniversityInventors: Tzong-Lin Wu, Hsu-Wei Liu, Chi-Hsuan Cheng, Po-Jui Li
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Publication number: 20240128947Abstract: An in-phase noise suppression device includes a signal transmitting unit and a grounding unit. The signal transmitting unit includes a number (N) of signal transmitting circuits, where N?3. Each of the signal transmitting circuits has an input terminal and an output terminal, receives a level signal at the input terminal thereof, and outputs the level signal at the output terminal thereof. The grounding unit includes a grounding circuit that is connected to the signal transmitting unit. The level signals respectively received by the signal transmitting circuits at the input terminals thereof, when being respectively transmitted along the signal transmitting circuits, generate at least two balanced digital signals and in-phase noise. The signal transmitting unit and the grounding circuit cooperatively constitute a noise suppression device so as to suppress the in-phase noise generated in the signal transmitting circuits.Type: ApplicationFiled: October 12, 2023Publication date: April 18, 2024Inventors: Chi-Hsuan CHENG, Yang-Chih HUANG
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Publication number: 20230337551Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a first spin orbit torque (SOT) layer on the MTJ, forming an inter-metal dielectric (IMD) layer around the first SOT layer, forming a second SOT layer on the IMD layer, forming a first hard mask on the second SOT layer, patterning the first hard mask along a first direction, and then patterning the first hard mask along a second direction.Type: ApplicationFiled: May 13, 2022Publication date: October 19, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jia-Rong Wu, Chi-Hsuan Cheng, Rai-Min Huang, Po-Kai Hsu
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Publication number: 20220216578Abstract: The invention discloses a filter device. The filter device comprises a substrate, at least one transmission conductor, and a reference conductor having a slotted structure. The substrate is provided at a first surface thereof with the transmission conductor, and provided at a second surface thereof with the reference conductor. The slotted structure comprises a frame portion, a slotted portion, and a hollow portion. The slotted portion surrounds the frame portion, and the hollow portion is formed in the frame portion. At least one impedance unit is configured on the frame portion. The equivalent filter circuit of the filter device is formed between the transmission conductor, the slotted structure, the reference conductor, and the impedance unit. Thereby, the equivalent filter circuit absorbs at least one noise at at least one specific frequency by the impedance unit to avoid the noise reflected to affect the transmission quality of signal.Type: ApplicationFiled: December 10, 2021Publication date: July 7, 2022Inventors: TZONG-LIN WU, HSU-WEI LIU, CHI-HSUAN CHENG, PO-JUI LI
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Publication number: 20210273089Abstract: A semiconductor device includes a substrate having at least two fins thereon and an isolation trench between the at least two fins; and an isolation structure in the isolation trench. The isolation structure consists of a liner layer covering a lower sidewall of each of the at least two fins and a bottom surface of the isolation trench, and a stress-buffer film on the liner layer. The stress-buffer film is a silicon suboxide film of formula SiOy, wherein y<2.Type: ApplicationFiled: May 17, 2021Publication date: September 2, 2021Inventors: Shih-Wei Su, Hao-Hsuan Chang, Chih-Wei Chang, Chi-Hsuan Cheng, Ting-An Chien, Bin-Siang Tsai
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Patent number: 11043596Abstract: A method for forming a semiconductor device is disclosed. A substrate having at least two fins thereon and an isolation trench between the at least two fins is provided. A liner layer is then deposited on the substrate. The liner layer conformally covers the two fins and interior surface of the isolation trench. A stress-buffer film is then deposited on the liner layer. The stress-buffer film completely fills a lower portion that is located at least below half of a trench depth of the isolation trench. A trench-fill oxide layer is then deposited to completely fill an upper portion of the isolation trench.Type: GrantFiled: June 25, 2019Date of Patent: June 22, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Wei Su, Hao-Hsuan Chang, Chih-Wei Chang, Chi-Hsuan Cheng, Ting-An Chien, Bin-Siang Tsai
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Publication number: 20200411681Abstract: A method for forming a semiconductor device is disclosed. A substrate having at least two fins thereon and an isolation trench between the at least two fins is provided. A liner layer is then deposited on the substrate. The liner layer conformally covers the two fins and interior surface of the isolation trench. A stress-buffer film is then deposited on the liner layer. The stress-buffer film completely fills a lower portion that is located at least below half of a trench depth of the isolation trench. A trench-fill oxide layer is then deposited to completely fill an upper portion of the isolation trench.Type: ApplicationFiled: June 25, 2019Publication date: December 31, 2020Inventors: Shih-Wei Su, Hao-Hsuan Chang, Chih-Wei Chang, Chi-Hsuan Cheng, Ting-An Chien, Bin-Siang Tsai
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Patent number: 10446682Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.Type: GrantFiled: January 9, 2019Date of Patent: October 15, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chi-Hsuan Cheng, Cheng-Pu Chiu, Yu-Chih Su, Chih-Yi Wang, Chin-Yang Hsieh, Tien-Shan Hsu, Yao-Jhan Wang
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Patent number: 10396419Abstract: The present invention provides a common-mode signal absorber, which comprises an impedance-matching network and a common-mode signal reflection circuit. A differential-mode signal is inputted into input ends of the impedance-matching network, and outputted from output ends of the common-mode signal reflection circuit. When a common-mode signal is inputted into the common-mode signal absorber, the common-mode signal reflection circuit is for reflecting the common-mode signal within a specific frequency band. Afterward, the reflection of the common-mode signal within the specific frequency band will be absorbed by an impedance element of the impedance-matching network. Thus, the common-mode signal within the specific frequency band may be absorbed by the impedance-matching network so as to avoid to interfere signals transmitted on a communication system.Type: GrantFiled: January 7, 2019Date of Patent: August 27, 2019Assignee: National Taiwan UniversityInventors: Tzong-Lin Wu, Po-Jui Li, Ying-Cheng Tseng, Chi-Hsuan Cheng
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Publication number: 20190148550Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.Type: ApplicationFiled: January 9, 2019Publication date: May 16, 2019Inventors: Chi-Hsuan Cheng, Cheng-Pu Chiu, Yu-Chih Su, Chih-Yi Wang, Chin-Yang Hsieh, Tien-Shan Hsu, Yao-Jhan Wang
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Publication number: 20190140333Abstract: The present invention provides a common-mode signal absorber, which comprises an impedance-matching network and a common-mode signal reflection circuit. A differential-mode signal is inputted into input ends of the impedance-matching network, and outputted from output ends of the common-mode signal reflection circuit. When a common-mode signal is inputted into the common-mode signal absorber, the common-mode signal reflection circuit is for reflecting the common-mode signal within a specific frequency band. Afterward, the reflection of the common-mode signal within the specific frequency band will be absorbed by an impedance element of the impedance-matching network. Thus, the common-mode signal within the specific frequency band may be absorbed by the impedance-matching network so as to avoid to interfere signals transmitted on a communication system.Type: ApplicationFiled: January 7, 2019Publication date: May 9, 2019Inventors: TZONG-LIN WU, PO-JUI LI, YING-CHENG TSENG, CHI-HSUAN CHENG
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Patent number: 10283415Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.Type: GrantFiled: September 16, 2018Date of Patent: May 7, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Te-Chang Hsu, An-Chi Liu, Nan-Yuan Huang, Yu-Chih Su, Cheng-Pu Chiu, Tien-Shan Hsu, Chih-Yi Wang, Chi-Hsuan Cheng
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Publication number: 20190103492Abstract: A method for forming epitaxial material on base material includes forming a stress cap layer on a base layer of a first semiconductor material. Then, a stress is induced on the base layer, wherein the stress is a tensile stress or a compressive stress. The stress cap layer is removed. An epitaxial layer of a second semiconductor material is formed on the base layer, wherein the second semiconductor material is different from the first semiconductor material.Type: ApplicationFiled: October 2, 2017Publication date: April 4, 2019Applicant: United Microelectronics Corp.Inventors: Cheng-Pu Chiu, Pei-Yu Chen, Shih-Min Lu, Ming-Yueh Tsai, Yung-Sung Lin, Te-Chang Hsu, Chih-Yi Wang, Chi-Hsuan Cheng, Sheng-Chen Chung, Yao-Jhan Wang
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Publication number: 20190080968Abstract: A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the fin elements is silicon. Etch residues are formed on the fin elements after the silicon substrate is etched. After that, a flush step is performed on the fin elements by flushing the surface of each of the fin elements with fluorocarbons. The etch residues on the fin elements are removed by the flush step. After the flush step, a strip step is performed on the fin elements by treating the surface of each of the fin elements with oxygen plasma.Type: ApplicationFiled: September 10, 2017Publication date: March 14, 2019Inventors: Chih-Yi Wang, Tien-Shan Hsu, Yu-Chih Su, Chi-Hsuan Cheng, Cheng-Pu Chiu, Te-Chang Hsu, Chin-Yang Hsieh, An-Chi Liu, Kuan-Lin Chen, Yao-Jhan Wang
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Patent number: 10217866Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.Type: GrantFiled: September 6, 2017Date of Patent: February 26, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chi-Hsuan Cheng, Cheng-Pu Chiu, Yu-Chih Su, Chih-Yi Wang, Chin-Yang Hsieh, Tien-Shan Hsu, Yao-Jhan Wang
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Patent number: 10211107Abstract: A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the fin elements is silicon. Etch residues are formed on the fin elements after the silicon substrate is etched. After that, a flush step is performed on the fin elements by flushing the surface of each of the fin elements with fluorocarbons. The etch residues on the fin elements are removed by the flush step. After the flush step, a strip step is performed on the fin elements by treating the surface of each of the fin elements with oxygen plasma.Type: GrantFiled: September 10, 2017Date of Patent: February 19, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Yi Wang, Tien-Shan Hsu, Yu-Chih Su, Chi-Hsuan Cheng, Cheng-Pu Chiu, Te-Chang Hsu, Chin-Yang Hsieh, An-Chi Liu, Kuan-Lin Chen, Yao-Jhan Wang
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Patent number: 10211496Abstract: The present invention provides a common-mode signal absorber, which comprises an impedance-matching network and a common-mode signal reflection circuit. A differential-mode signal is inputted into input ends of the impedance-matching network, and outputted from output ends of the common-mode signal reflection circuit. When a common-mode signal is inputted into the common-mode signal absorber, the common-mode signal reflection circuit is for reflecting the common-mode signal within a specific frequency band. Afterward, the reflection of the common-mode signal within the specific frequency band will be absorbed by an impedance element of the impedance-matching network. Thus, the common-mode signal within the specific frequency band may be absorbed by the impedance-matching network so as to avoid to interfere signals transmitted on a communication system.Type: GrantFiled: May 3, 2017Date of Patent: February 19, 2019Assignee: National Taiwan UniversityInventors: Tzong-Lin Wu, Po-Jui Li, Ying-Cheng Tseng, Chi-Hsuan Cheng
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Publication number: 20190043760Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.Type: ApplicationFiled: September 16, 2018Publication date: February 7, 2019Inventors: Te-Chang Hsu, An-Chi Liu, Nan-Yuan Huang, Yu-Chih Su, Cheng-Pu Chiu, Tien-Shan Hsu, Chih-Yi Wang, Chi-Hsuan Cheng
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Publication number: 20190027603Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.Type: ApplicationFiled: September 6, 2017Publication date: January 24, 2019Inventors: Chi-Hsuan Cheng, Cheng-Pu Chiu, Yu-Chih Su, Chih-Yi Wang, Chin-Yang Hsieh, Tien-Shan Hsu, Yao-Jhan Wang
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Patent number: 10109531Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A topmost portion of the first bump is lower than the base, and a width of the first bump is larger than a width of each of the fin shaped structures.Type: GrantFiled: June 8, 2017Date of Patent: October 23, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Te-Chang Hsu, An-Chi Liu, Nan-Yuan Huang, Yu-Chih Su, Cheng-Pu Chiu, Tien-Shan Hsu, Chih-Yi Wang, Chi-Hsuan Cheng