Abstract: A pre-forming adaptor for semiconductor packaging includes at least one lead frame and at least one packaging enclosure bonded with the at least one lead frame. Each of the lead frame and the packaging enclosure has a pre-forming shape provided according to a predetermined package outline of a semiconductor device.

Abstract: A die suction assistance device is provided to a wafer. The wafer is diced into multiple dies, and a tape is taped on a bottom side of the wafer. The die suction assistance device includes a platform and multiple support structures mounted in the platform. Multiple air ducts are formed among adjacent support structures. When the wafer is air-tightly mounted on the platform, the wafer is supported by the support structures. When an external vacuum device vacuums air out of the platform, a vacuum environment with negative pressure is created in the air ducts. This allows the tape to partially separate from a backside of each of the dies towards the air ducts, and allows the dies to be picked up respectively by a suction nozzle with less chance of being damaged, securing integrities of dies.

Abstract: A side wettable package includes a molding compound, a chip and multiple conductive pads exposed from a bottom surface of the molding compound. The conductive pads include peripheral conductive pads arranged near a side wall of the molding compound. Each of the peripheral conductive pads is over etched to form an undercut. When the side wettable package is connected to a circuit board via solder, the solder ascends to the undercut of the peripheral conductive pads for improving connection yield and facilitating inspection of soldering quality.

Abstract: The present invention provides a wafer level chip scale package (WLCSP) unit; the WLCSP unit includes a die, a dielectric layer, and a bottom metal layer; the die has a substrate and an active surface; multiple pads are mounted on the active surface, and a soldering layer is mounted on a surface of each of the pads; the dielectric layer covers an upper part of four lateral surfaces of the die, exposing a lower part of the four lateral surfaces of the die; the bottom metal layer is mounted on a bottom surface of the substrate; the bottom metal layer protects a bottom surface of the dies, dissipates heat generated by the dies, and also protects the dies from external electromagnetic interferences (EMI).

Abstract: A semiconductor package includes a molding compound, a chip and a conductive pad, wherein the chip is electrically connected to the conductive pad and both are encapsulated in the molding compound. An anchor flange is formed around a top surface of the conductive pad by over plating. When the conductive pad is embedded in the molding compound, the anchor flange engages the molding compound to prevent the conductive pad from separation. Bottoms of a chip and the conductive pad are exposed from the molding compound for electrically soldering to a circuit board.

Abstract: A metal oxide semiconductor (MOS) with multiple drain vias includes a semiconductor substrate, which is divided into a gate region, a source region and a drain region. On the same surface of the semiconductor substrate in the gate region, a connection layer is formed in the source region and the drain region with a low-resistance metal material. A plurality of conductive elements, such as solder balls, can be directly arranged on the connection layer, so that the MOS can be soldered to the circuit board through the conductive elements distributed on the same surface. In the drain region, there are a plurality of vias. The inside of each via is filled with the connection layer and extends to the inside of the semiconductor substrate. With the aforementioned structure, the MOS has the advantage of low on-resistance RDS(ON).

Abstract: A semiconductor package with improved solderability at sidewall includes a chip, a molding compound encapsulating the chip, and multiple leads distributed at sidewalls of the semiconductor package. The leads are formed as a conductive layer that is electrically connected to bonding pads of the chip. Each of the leads has a stepped surface exposed from the molding compound, wherein the stepped surface is shaped by two sequentially overlapped photoresist layers. The stepped surface of each lead allows to accommodate more solder to enhance the reliability of a solder joint between the semiconductor and a printed circuit board. Therefore, the solder joints of the semiconductor package are easily inspected by automatic optical inspection (AOI) equipment.

Abstract: A package device preventing solder overflow provides a space or structure to limit the location of the solder when dispensing the solder. The package device includes a die, an anti-overflow layer, a first pin, a second pin, and a package body. The die has an electrode pad. The anti-overflow layer is disposed on a top surface of the electrode pad and has an opening to expose the top surface of the electrode pad. The first pin is connected to the die. The second pin is soldered to the electrode pad of the die through the opening of the anti-overflow layer. The package body covers the die.

Abstract: A thin semiconductor packaging unit includes a semiconductor die, a mold, two contact bulks, a first bridge layer, a second bride layer, and two insulation layers; the mold covers a side surface of the semiconductor die; the mold includes two sides, and each of the sides includes at least one first contact area; the two contact bulks are respectively mounted on the two sides of the mold; each of the contact bulks includes at least one second contact area connecting the at least one first contact area; the first bridge layer connects the top electrode of the semiconductor die to one of the contact bulks; the second bride layer connects the bottom electrode of the semiconductor die to the other one of the contact bulks; the two insulation layers respectively cover the first bridge layer and the second bridge layer; the present invention dissipates heat efficiently.

Abstract: A method for manufacturing a packaged component with a composite pin structure has: dividing a substrate into a body area and a pin area, wherein a chip is arranged on the body area of the substrate and is electrically connected to conductive layers on the opposite surfaces of the substrate. The pin area is pre-defined with multiple parallel pin positions. After the electrical connection of the chip is completed in the body area, a cutting tool is used to cut along the peripheries of the body area and the pin positions to obtain a packaged component body and multiple pins. Each of the pins is integrally formed by the substrate of the packaged component body without using a conventional lead frame.

Abstract: A semiconductor package element includes a die, a passive layer, a conductive structure and an encapsulation layer. The die includes a first surface, a second surface and a third surface. The second surface is opposite to the first surface. The third surface is connected between the first surface and the second surface. The passive layer is disposed on the first surface and formed with a hole. The conductive structure is electrically coupled to the die through the hole. The encapsulation layer covers the first surface and the third surface of the die, wherein the passive layer is embedded in the encapsulation layer, a portion of the conductive structure is embedded in the encapsulation layer, and the other portion of the conductive structure protrudes from an etched surface of the encapsulation layer, the etched surface is formed by plasma etching.

Abstract: A semiconductor package structure, including a lead frame, a die disposed on the front side of the lead frame, and a molding piece disposed on the lead frame and encapsulates the die, wherein the lead frame is provided with two extension portions extending respectively from two sides of the molding piece, and the extension portion is provided with recessed front surface and back surface on which a plating layer is formed.

Abstract: A semiconductor package includes a molding compound, a chip and a conductive pad, wherein the chip is electrically connected to the conductive pad and both are encapsulated in the molding compound. An anchor flange is formed around a top surface of the conductive pad by over plating. When the conductive pad is embedded in the molding compound, the anchor flange engages the molding compound to prevent the conductive pad from separation. Bottoms of a chip and the conductive pad are exposed from the molding compound for electrically soldering to a circuit board.

Abstract: The invention describes a fabricating method for fabricating semiconductor package device which includes the following steps: providing a wafer having a plurality of dies, wherein each of the dies is provided on a top surface thereof with a middle electric conducting structure and a solder ball; forming a molding structure having a flat top surface on a top side of the wafer; removing a part of the molding structure and exposing a part of each of the solder ball by plasma etching; performing a dicing process along a boundary of each of the dies to separate each of the dies so that the semiconductor package device is thus obtained.

Abstract: A semiconductor package element includes a die, a passive layer, a conductive structure and an encapsulation layer. The die includes a first surface, a second surface and a third surface. The second surface is opposite to the first surface. The third surface is connected between the first surface and the second surface. The passive layer is disposed on the first surface and formed with a hole. The conductive structure is electrically coupled to the die through the hole. The encapsulation layer covers the first surface and the third surface of the die, wherein the passive layer is embedded in the encapsulation layer, a portion of the conductive structure is embedded in the encapsulation layer, and the other portion of the conductive structure protrudes from an etched surface of the encapsulation layer, the etched surface is formed by plasma etching.

Abstract: The present invention includes a chip, a plastic film layer, and an electroplated layer. A front side and a back side of the chip each comprises a signal contact. The plastic film layer covers the chip and includes a first via and a second via. The first via is formed adjacent to the chip, and the second via is formed extending to the signal contact of the front side. A conductive layer is added in the first and the second via. The conductive layer in the second via is electrically connected to the signal contact of the front side. Through the electroplated layer, the signal contact on the back side is electrically connected to the conductive layer in the first via. The conductive layer protrudes from the plastic film layer as conductive terminals. The present invention achieves electrical connection of the chip without using expensive die bonding materials.

Abstract: A side wettable package includes a molding compound, a chip and multiple conductive pads exposed from a bottom surface of the molding compound. The conductive pads include peripheral conductive pads arranged near a side wall of the molding compound. Each of the peripheral conductive pads is over etched to form an undercut. When the side wettable package is connected to a circuit board via solder, the solder ascends to the undercut of the peripheral conductive pads for improving connection yield and facilitating inspection of soldering quality.

Abstract: A side wettable package includes a molding compound, a chip and multiple conductive pads exposed from a bottom surface of the molding compound. The conductive pads include peripheral conductive pads arranged near a side wall of the molding compound. Each of the peripheral conductive pads is over etched to form an undercut. When the side wettable package is connected to a circuit board via solder, the solder ascends to the undercut of the peripheral conductive pads for improving connection yield and facilitating inspection of soldering quality.

Abstract: A thin semiconductor package includes a die paddle and multiple lead fingers made of a metal substrate. A die paddle electroplating layer and a lead finger electroplating layer are formed on the surface of the die paddle and surfaces of the lead fingers, respectively. A die is provided on the die paddle electroplating layer and is electrically connected to the lead finger electroplating layer. The die paddle, the die and the lead fingers are encapsulated by a molding compound. The lower surfaces of the die paddle and the lead fingers are exposed on the bottom surface of the molding compound. The die paddles and the lead fingers are formed by etching the metal substrate instead without using a lead frame.

Abstract: A semiconductor package includes a molding compound, a chip and a conductive pad, wherein the chip is electrically connected to the conductive pad and both are encapsulated in the molding compound. An anchor flange is formed around a top surface of the conductive pad by over plating. When the conductive pad is embedded in the molding compound, the anchor flange engages the molding compound to prevent the conductive pad from separation. Bottoms of a chip and the conductive pad are exposed from the molding compound for electrically soldering to a circuit board.