Abstract: An inductor is disclosed, the inductor comprising: a T-shaped magnetic core, being made of a material comprising an annealed soft magnetic metal material and having a base and a pillar integrally formed with the base, wherein ?C×Hsat?1800, where ?C is a permeability of the T-shaped magnetic core, and Hsat (Oe) is a strength of the magnetic field at 80% of ?C0, where ?C0 is the permeability of the T-shaped magnetic core when the strength of the magnetic field is 0.

Abstract: A semiconductor light emitting device includes a substrate, a first epitaxial structure and a second epitaxial structure, a connecting layer, a first electrode structure, a second electrode structure, and a third electrode structure. The first epitaxial structure and the second epitaxial structure are on the substrate side by side. The connecting layer is between the first epitaxial structure and the substrate, between the second epitaxial structure and the substrate, and between the first epitaxial structure and the second epitaxial structure. The first electrode structure is on the first epitaxial structure away from the substrate. The second electrode structure is on the second epitaxial structure away from the substrate. The third electrode structure is connected to the connecting layer.

Abstract: A chip package structure includes a substrate having a first surface and a second surface being opposite surfaces of the substrate; a housing disposed on the first surface of the substrate and enclosing a chip region; and a chip set disposed in the chip region and electrically connected to the substrate. The chip set includes a first chip and a second chip, and an active surface of the second chip faces the active surface of the first chip.

Abstract: A semiconductor laser includes a base, an epitaxial structure on the base, and a first electrode and a second electrode on the epitaxial structure. The epitaxial structure includes a first semiconductor structure on the base, a second semiconductor structure on the first semiconductor structure, an intermediate layer on the second semiconductor structure, a third semiconductor structure on the intermediate layer, a current-confining layer in the third semiconductor structure, a fourth semiconductor structure on the third semiconductor structure, and an active structure between the third semiconductor structure and the fourth semiconductor structure. The first electrode and the second electrode are on the fourth semiconductor structure, wherein a part of the first electrode passes through the fourth semiconductor structure, the active structure, the current-confining layer and the third semiconductor structure and is connected to the intermediate layer.

Abstract: An exemplary integrated circuit comprises: a first device gate disposed over the first device region, the first device gate comprising a first interfacial layer and a first dielectric layer; a second device gate disposed over the second device region, the second device gate comprising a second interfacial layer and a second dielectric layer; and a third device gate disposed over the third device region, the third device gate comprising a third interfacial layer and a third dielectric layer, wherein the first interfacial layer, the second interfacial layer, and the third interfacial layer are different from each other in at least one of a thickness and an interfacial material.

Abstract: The present disclosure provides an FET structure including a transistor of a first conductive type. The transistor includes a substrate having a region of a second conductive type, a channel between source and drain, and a gate over the channel. The channel includes dopants of the first conductive type. The gate includes a work function setting layer of the second conductive type. The present disclosure also provides a method for manufacturing an FET with multi-threshold voltages scheme. The method includes exposing channels of a first transistor of a first conductive type and a first transistor of a second conductive type from a first mask, doping the channels with dopants of the first conductive type, exposing channels of a second transistor of the first conductive type and a second conductive type from a second mask, and doping the channels with dopants of the second conductive type.

Abstract: The present disclosure provides an FET structure including a transistor of a first conductive type. The transistor includes a substrate having a region of a second conductive type, a channel between source and drain, and a gate over the channel. The channel includes dopants of the first conductive type. The gate includes a work function setting layer of the second conductive type. The present disclosure also provides a method for manufacturing an FET with multi-threshold voltages scheme. The method includes exposing channels of a first transistor of a first conductive type and a first transistor of a second conductive type from a first mask, doping the channels with dopants of the first conductive type, exposing channels of a second transistor of the first conductive type and a second conductive type from a second mask, and doping the channels with dopants of the second conductive type.

Abstract: The present disclosure provides an FET structure including a transistor of a first conductive type. The transistor includes a substrate having a region of a second conductive type, a channel between source and drain, and a gate over the channel. The channel includes dopants of the first conductive type. The gate includes a work function setting layer of the second conductive type. The present disclosure also provides a method for manufacturing an FET with multi-threshold voltages scheme. The method includes exposing channels of a first transistor of a first conductive type and a first transistor of a second conductive type from a first mask, doping the channels with dopants of the first conductive type, exposing channels of a second transistor of the first conductive type and a second conductive type from a second mask, and doping the channels with dopants of the second conductive type.

Abstract: The present disclosure provides an FET structure including a transistor of a first conductive type. The transistor includes a substrate having a region of a second conductive type, a channel between source and drain, and a gate over the channel. The channel includes dopants of the first conductive type. The gate includes a work function setting layer of the second conductive type. The present disclosure also provides a method for manufacturing an FET with multi-threshold voltages scheme. The method includes exposing channels of a first transistor of a first conductive type and a first transistor of a second conductive type from a first mask, doping the channels with dopants of the first conductive type, exposing channels of a second transistor of the first conductive type and a second conductive type from a second mask, and doping the channels with dopants of the second conductive type.

Abstract: An exemplary integrated circuit comprises: a first device gate disposed over the first device region, the first device gate comprising a first interfacial layer and a first dielectric layer; a second device gate disposed over the second device region, the second device gate comprising a second interfacial layer and a second dielectric layer; and a third device gate disposed over the third device region, the third device gate comprising a third interfacial layer and a third dielectric layer, wherein the first interfacial layer, the second interfacial layer, and the third interfacial layer are different from each other in at least one of a thickness and an interfacial material.

Abstract: A method including providing a substrate having a first region, a second region, and a third region defined thereupon. A first interfacial layer is formed over the first region, the second region, and the third region. The first interfacial layer is etched to remove a portion of the first interfacial layer from the first region and a portion of the first interfacial layer from the second region. Etching of the first interfacial layer defines a gate stack within the third region. After the etching of the first interfacial layer, a second interfacial layer is formed over at least a portion of the second region. The second interfacial layer is etched to define a gate stack within the second region. After the etching of the second interfacial layer, a third interfacial layer is formed on the substrate over at least a portion of the first region to define a gate stack within the first region.

Abstract: A method including providing a substrate having a first region, a second region, and a third region defined thereupon. A first interfacial layer is formed over the first region, the second region, and the third region. The first interfacial layer is etched to remove a portion of the first interfacial layer from the first region and a portion of the first interfacial layer from the second region. Etching of the first interfacial layer defines a gate stack within the third region. After the etching of the first interfacial layer, a second interfacial layer is formed over at least a portion of the second region. The second interfacial layer is etched to define a gate stack within the second region. After the etching of the second interfacial layer, a third interfacial layer is formed on the substrate over at least a portion of the first region to define a gate stack within the first region.

Abstract: An integrated circuit having multiple different device gate configurations and a method for fabricating the circuit are disclosed. An exemplary embodiment of forming the circuit includes receiving a substrate having a first device region, a second device region, and a third device region. A first interfacial layer is formed over at least a portion of each of the first device region, the second device region, and the third device region. The first interfacial layer is patterned to define a gate stack within the third device region. A second interfacial layer is formed over at least a portion of the second device region. The second interfacial layer is patterned to define a gate stack within the second device region. A third interfacial layer is formed over at least a portion of the first device region. The third interfacial layer defines a gate stack within the first device region.

Abstract: An integrated circuit having multiple different device gate configurations and a method for fabricating the circuit are disclosed. An exemplary embodiment of forming the circuit includes receiving a substrate having a first device region, a second device region, and a third device region. A first interfacial layer is formed over at least a portion of each of the first device region, the second device region, and the third device region. The first interfacial layer is patterned to define a gate stack within the third device region. A second interfacial layer is formed over at least a portion of the second device region. The second interfacial layer is patterned to define a gate stack within the second device region. A third interfacial layer is formed over at least a portion of the first device region. The third interfacial layer defines a gate stack within the first device region.

Abstract: A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region, the substrate having a front side and a backside. A co-implant process is performed along the backside of the substrate opposing a photosensitive element positioned along the front side of the substrate. The co-implant process utilizes a first pre-amorphization implant process that creates a pre-amorphization region. A dopant is then implanted wherein the pre-amorphization region retards or reduces the diffusion or tailing of the dopants into the photosensitive region. An anti-reflective layer, a color filter, and a microlens may also be formed over the co-implant region.

Abstract: A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region, the substrate having a front side and a backside. A co-implant process is performed along the backside of the substrate opposing a photosensitive element positioned along the front side of the substrate. The co-implant process utilizes a first pre-amorphization implant process that creates a pre-amorphization region. A dopant is then implanted wherein the pre-amorphization region retards or reduces the diffusion or tailing of the dopants into the photosensitive region. An anti-reflective layer, a color filter, and a microlens may also be formed over the co-implant region.

Abstract: A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region, the substrate having a front side and a backside. A co-implant process is performed along the backside of the substrate opposing a photosensitive element positioned along the front side of the substrate. The co-implant process utilizes a first pre-amorphization implant process that creates a pre-amorphization region. A dopant is then implanted wherein the pre-amorphization region retards or reduces the diffusion or tailing of the dopants into the photosensitive region. An anti-reflective layer, a color filter, and a microlens may also be formed over the co-implant region.

Abstract: A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region, the substrate having a front side and a backside. A co-implant process is performed along the backside of the substrate opposing a photosensitive element positioned along the front side of the substrate. The co-implant process utilizes a first pre-amorphization implant process that creates a pre-amorphization region. A dopant is then implanted wherein the pre-amorphization region retards or reduces the diffusion or tailing of the dopants into the photosensitive region. An anti-reflective layer, a color filter, and a microlens may also be formed over the co-implant region.

Abstract: A method is provided for improving Idsat in NMOS and PMOS transistors. A silicon nitride etch stop layer is deposited by a PECVD technique on STI and silicide regions and on sidewall spacers during a MOSFET manufacturing scheme. A dielectric layer is formed on the nitride and then contact holes are fabricated through the dielectric layer and nitride layer to silicide regions and are filled with a metal. For NMOS transistors, silane and NH3 flow rates and a 400° C. temperature are critical in improving NMOS short channel Idsat. Hydrogen content in the nitride is increased by higher NH3 and SiH4 flow rates but does not significantly degrade HCE and Vt. With PMOS transistors, deposition temperature is increased to 550° C. to reduce hydrogen content and improve HCE and Vt stability.

Abstract: A thermal oxidation method for forming a gate dielectric layer for use within a field effect transistor device employs a thermal oxidizing atmosphere comprising a halogen getter material. By employing the halogen getter material, the field effect transistor device is formed with enhanced performance, in particular with respect to negative bias temperature instability lifetime.