Patents by Inventor Chi-Hsun Lin
Chi-Hsun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12266573Abstract: In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a second semiconductor fin protruding above the isolation region; and a dielectric fin between the first semiconductor fin and the second semiconductor fin, the dielectric fin protruding above the isolation region, the dielectric fin including: a first layer including a first dielectric material having a first carbon concentration; and a second layer on the first layer, the second layer including a second dielectric material having a second carbon concentration, the second carbon concentration greater than the first carbon concentration.Type: GrantFiled: September 23, 2021Date of Patent: April 1, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi Chen Ho, Yiting Chang, Chi-Hsun Lin, Zheng-Yang Pan
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Publication number: 20250098276Abstract: Methods for forming a semiconductor device structure are described. The method includes forming first and second fin structures over a substrate and forming a dielectric wall between the first and second fin structures. The forming the dielectric wall includes depositing a first dielectric layer between the first and second fin structures, and a seam is formed in the first dielectric layer. The forming the dielectric wall further includes performing an anisotropic etch process to remove a portion of the first dielectric layer to expose the seam, performing an isotropic etch process to enlarge an opening of the seam, and the seam has a āVā shaped cross-sectional profile. The forming the dielectric wall further includes depositing a second dielectric layer between the first and second fin structures, and the seam is filled. The method further includes forming shallow trench isolation regions adjacent the first and second fin structures.Type: ApplicationFiled: September 15, 2023Publication date: March 20, 2025Inventors: Kai-Chun CHANG, Chi-Hsun LIN, Yi Chen HO, Hung Cheng LIN
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Publication number: 20240395631Abstract: Some implementations described herein provide a method that includes forming a set of fins of a device, where the set of fins comprises an isolation fin disposed between a first fin and a second fin of the set of fins. The method also includes forming an isolation structure on at least one side of the isolation fin, with the isolation fin providing electrical isolation between the first fin and the second fin of the set of fins. Additionally, or alternatively, some implementations described herein provide a method that includes forming a funnel-shaped isolation structure between a first set of fins and a second set of fins. Additionally, or alternatively, some implementations described herein provide a method that includes forming, after forming a first gate structure and a second gate structure, an isolation structure between the first gate structure and the second gate structure.Type: ApplicationFiled: July 30, 2024Publication date: November 28, 2024Inventors: Yi Chen HO, Yu-Chuan CHEN, Chieh CHENG, Chi-Hsun LIN, Zheng-Yang PAN, Shahaji B. MORE
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Publication number: 20240379450Abstract: In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a second semiconductor fin protruding above the isolation region; and a dielectric fin between the first semiconductor fin and the second semiconductor fin, the dielectric fin protruding above the isolation region, the dielectric fin including: a first layer including a first dielectric material having a first carbon concentration; and a second layer on the first layer, the second layer including a second dielectric material having a second carbon concentration, the second carbon concentration greater than the first carbon concentration.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Inventors: Yi Chen Ho, Yiting Chang, Chi-Hsun Lin, Zheng-Yang Pan
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Publication number: 20240278295Abstract: A method of cleaning includes placing a semiconductor device manufacturing tool component made of quartz on a support. A cleaning fluid inlet line is attached to a first open-ended tubular quartz projection extending from an outer main surface of the semiconductor device manufacturing tool component. A cleaning fluid is applied to the semiconductor device manufacturing tool component by introducing the cleaning fluid through the cleaning fluid inlet line and the tubular quartz projection.Type: ApplicationFiled: April 18, 2024Publication date: August 22, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chen HO, Chih Ping LIAO, Ker-Hsun LIAO, Chi-Hsun LIN
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Patent number: 12057351Abstract: Some implementations described herein provide a method that includes forming a set of fins of a device, where the set of fins comprises an isolation fin disposed between a first fin and a second fin of the set of fins. The method also includes forming an isolation structure on at least one side of the isolation fin, with the isolation fin providing electrical isolation between the first fin and the second fin of the set of fins. Additionally, or alternatively, some implementations described herein provide a method that includes forming a funnel-shaped isolation structure between a first set of fins and a second set of fins. Additionally, or alternatively, some implementations described herein provide a method that includes forming, after forming a first gate structure and a second gate structure, an isolation structure between the first gate structure and the second gate structure.Type: GrantFiled: March 10, 2022Date of Patent: August 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi Chen Ho, Yu-Chuan Chen, Chieh Cheng, Chi-Hsun Lin, Zheng-Yang Pan, Shahaji B. More
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Publication number: 20240247700Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.Type: ApplicationFiled: April 4, 2024Publication date: July 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chen HO, Chih Ping LIAO, Chien Ting LIN, Jie-Ying YANG, Wei-Ming WANG, Ker-Hsun LIAO, Chi-Hsun LIN
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Patent number: 12000455Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.Type: GrantFiled: March 10, 2022Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi Chen Ho, Chih Ping Liao, Chien Ting Lin, Jie-Ying Yang, Wei-Ming Wang, Ker-Hsun Liao, Chi-Hsun Lin
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Patent number: 11986869Abstract: A method of cleaning includes placing a semiconductor device manufacturing tool component made of quartz on a support. A cleaning fluid inlet line is attached to a first open-ended tubular quartz projection extending from an outer main surface of the semiconductor device manufacturing tool component. A cleaning fluid is applied to the semiconductor device manufacturing tool component by introducing the cleaning fluid through the cleaning fluid inlet line and the tubular quartz projection.Type: GrantFiled: June 6, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi Chen Ho, Chih Ping Liao, Ker-hsun Liao, Chi-Hsun Lin
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Publication number: 20230390813Abstract: A method of cleaning includes placing a semiconductor device manufacturing tool component made of quartz on a support. A cleaning fluid inlet line is attached to a first open-ended tubular quartz projection extending from an outer main surface of the semiconductor device manufacturing tool component. A cleaning fluid is applied to the semiconductor device manufacturing tool component by introducing the cleaning fluid through the cleaning fluid inlet line and the tubular quartz projection.Type: ApplicationFiled: June 6, 2022Publication date: December 7, 2023Inventors: Yi Chen HO, Chih Ping LIAO, Ker-hsun LIAO, Chi-Hsun LIN
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Publication number: 20230343559Abstract: Some implementations described herein provide techniques and apparatuses for overcoming forces that may deflect an injector nozzle into an interior wall of a thin-film furnace. The implementations include a fixture that is coupled to the injector nozzle. The fixture is configurable to lock to a selected property of the injector nozzle to maintain, between a portion of the injector nozzle and the interior wall, a gap. In this way, the portion of the injector nozzle is prevented from colliding with the interior wall and dislodging particulates that may contaminate semiconductor product fabricated using the thin-film furnace.Type: ApplicationFiled: April 21, 2022Publication date: October 26, 2023Inventors: Yi Chen HO, Chih Ping LIAO, Shih Hao YANG, Wei-Ming WANG, Chien Ting LIN, Jie-Ying YANG, Chih-Che TANG, Kuo Kang TENG, Ming-Hui YU, Ker-hsun LIAO, Chi-Hsun LIN
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Publication number: 20230287952Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.Type: ApplicationFiled: March 10, 2022Publication date: September 14, 2023Inventors: Yi Chen HO, Chih Ping LIAO, Chien Ting LIN, Jie-Ying YANG, Wei-Ming WANG, Ker-Hsun LIAO, Chi-Hsun LIN
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Publication number: 20230154803Abstract: Some implementations described herein provide a method that includes forming a set of fins of a device, where the set of fins comprises an isolation fin disposed between a first fin and a second fin of the set of fins. The method also includes forming an isolation structure on at least one side of the isolation fin, with the isolation fin providing electrical isolation between the first fin and the second fin of the set of fins. Additionally, or alternatively, some implementations described herein provide a method that includes forming a funnel-shaped isolation structure between a first set of fins and a second set of fins. Additionally, or alternatively, some implementations described herein provide a method that includes forming, after forming a first gate structure and a second gate structure, an isolation structure between the first gate structure and the second gate structure.Type: ApplicationFiled: March 10, 2022Publication date: May 18, 2023Inventors: Yi Chen HO, Yu-Chuan CHEN, Chieh CHENG, Chi-Hsun LIN, Zheng-Yang PAN, Shahaji B. MORE
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Publication number: 20230008893Abstract: In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a second semiconductor fin protruding above the isolation region; and a dielectric fin between the first semiconductor fin and the second semiconductor fin, the dielectric fin protruding above the isolation region, the dielectric fin including: a first layer including a first dielectric material having a first carbon concentration; and a second layer on the first layer, the second layer including a second dielectric material having a second carbon concentration, the second carbon concentration greater than the first carbon concentration.Type: ApplicationFiled: September 23, 2021Publication date: January 12, 2023Inventors: Yi Chen Ho, Yiting Chang, Chi-Hsun Lin, Zheng-Yang Pan