Abstract: A semiconductor structure includes: a first semiconductor die or wafer including a first bonding crack detection structure portion including discrete bonding crack detection structure portions that are electrically isolated, and a second semiconductor die or wafer bonded to the first semiconductor die, the second semiconductor die or wafer including a second bonding crack detection structure portion including discrete bonding crack detection structure portions that are electrically isolated, wherein the first bonding crack detection structure portion and the second bonding crack detection structure portion are bonded together to form a bonding crack detection structure.

Abstract: A method of testing a semiconductor package includes: attaching a charge measurement unit to a carrier substrate; forming a first metallization layer over the charge measurement unit, wherein the forming of the first metallization layer induces first charges to accumulate on the charge measurement unit; performing a first test against the charge measurement unit to determine whether breakdown occurs in the charge measurement unit; and in response to determining that no breakdown occurs in the charge measurement unit, forming a second metallization layer over the first metallization layer.

Abstract: A hydrophobic metal organic framework (MOF) material includes one or plural metal ion(s), plural multidentates and plural hydrophobic groups. The multidentates are coordinately bonded to the metal ion(s). The multidentates include oxygen atoms and/or nitrogen atoms. The hydrophobic groups form bonds with the oxygen atoms and/or nitrogen atoms on the multidentates, and the hydrophobic groups jointly form 3-dimensional network structure.

Abstract: Height adjustable seat posts for bicycles are described herein. An example height adjustable seat post includes an upper tube and a lower tube configured in a telescopic arrangement. The height adjustable seat post also includes a shaft coupled to the lower tube and extending into the upper tube a piston assembly coupled to the shaft and disposed in the upper tube. The piston assembly includes a piston dividing the upper tube into a first chamber and a second chamber. The first and second chambers are filled with fluid. The piston assembly includes a valve operable between a closed state in which the fluid is blocked from flowing between the first and second chambers and an open state to enable the fluid to flow between the first and second chambers. The height adjustable seat post also includes a solenoid to control the valve.

Abstract: A semiconductor includes a first substrate having a device region and a ring region surrounding the device region, a first interconnect structure over the first substrate, the first interconnect structure including a first via tower and a second via tower, a first bonding layer over the first interconnect structure and including a first metal bonding feature, a second bonding layer over the first bonding layer and including a second metal bonding feature in contact with the first metal bonding feature, and a second interconnect structure over the second bonding layer and including a third via tower extending through the second interconnect structure and disposed directly over the ring region. The first via tower is electrically coupled to the second via tower by a first metal line. The first via tower is electrically coupled to the third via tower by the first metal bonding feature and the second metal bonding feature.

Abstract: Height adjustable seat posts for bicycles are described herein. An example height adjustable seat post includes an upper tube and a lower tube configured in a telescopic arrangement. The height adjustable seat post also includes a shaft coupled to the lower tube and extending into the upper tube a piston assembly coupled to the shaft and disposed in the upper tube. The piston assembly includes a piston dividing the upper tube into a first chamber and a second chamber. The first and second chambers are filled with fluid. The piston assembly includes a valve operable between a closed state in which the fluid is blocked from flowing between the first and second chambers and an open state to enable the fluid to flow between the first and second chambers. The height adjustable seat post also includes a solenoid to control the valve.

Abstract: A package includes a package substrate, an interposer over and bonded to the package substrate, a first wafer over and bonding to the interposer, and a second wafer over and bonding to the first wafer. The first wafer has independent passive device dies therein. The second wafer has active device dies therein.

Abstract: A method of testing a semiconductor package includes: forming a charge measurement unit over a carrier substrate; forming a first dielectric layer over the charge measurement unit; forming a first metallization layer over the dielectric layer, wherein the forming of the first metallization layer induces first charges to accumulate on the charge measurement unit; performing a first test against the charge measurement unit to determine whether breakdown occurs in the charge measurement unit; and in response to determining that no breakdown occurs in the charge measurement unit, forming a second dielectric layer over the first metallization layer.

Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.

Abstract: A semiconductor structure includes a first die; a molding surrounding the first die; a redistribution layer (RDL) disposed under the first die and the molding, and including a plurality of first conductive pads and a dielectric layer surrounding the plurality of first conductive pads; a second die disposed under the RDL, and including a plurality of first die pads over the second die; and a plurality of first conductive bumps disposed between the RDL and the second die, wherein each of the plurality of first conductive bumps is electrically coupled with corresponding one of the plurality of first die pads and corresponding one of the plurality of first conductive pads, the plurality of first die pads are respectively arranged at corners of the second die, and the plurality of first conductive bumps are electrically connected in series.

Abstract: A package includes a package substrate, an interposer over and bonded to the package substrate, a first wafer over and bonding to the interposer, and a second wafer over and bonding to the first wafer. The first wafer has independent passive device dies therein. The second wafer has active device dies therein.

Abstract: An embodiment includes a first package component including a first integrated circuit die and a first encapsulant at least partially surrounding the first integrated circuit die. The device also includes a redistribution structure on the first encapsulant and coupled to the first integrated circuit die. The device also includes a first thermal module coupled to the first integrated circuit die. The device also includes a second package component bonded to the first package component, the second package component including a power module attached to the first package component, the power module including active devices. The device also includes a second thermal module coupled to the power module. The device also includes a mechanical brace extending from a top surface of the second thermal module to a bottom surface of the first thermal module, the mechanical brace physically contacting the first thermal module and the second thermal module.

Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.

Abstract: The airport ground collision alerting system comprises an automatic dependent surveillance-broadcast, ADS-B, receiver; a first database coupled to the ADS-B receiver and configured for look-up of aircraft type data based on aircraft ID data received via the ADS-B receiver and for storing aircraft position and heading data received via the ADS-B receiver; a second database configured to store digital map data for one or more airports; a processor coupled to the first and second databases and an application programming interface, API, configured to couple the airport ground collision alerting system to a display device.

Abstract: Real-time subpixel detection and classification is provided. The method comprises receiving input of a spectral library of targets, a multi-spectral image cube, and a list of background image samples. A candidate ground spatial distance (GSD) cell within the multi-spectral image cube is selected for spectral demixing. The spectrally demixed candidate GSD cell is compared against the spectral library and the list of background image samples. A determination is made whether the candidate GSD cell contains an identifiable target. The candidate GSD cell is labeled unknown if it does not resemble a target in the spectral library nor a sample in the list of potential background image sample. Local global reconciliation is applied to the candidate GSD cell to reject false detections of non-targets and confirm true detection of targets. Detected targets from the candidate GSD cell or an unknown are output in real-time.

Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.

Abstract: An embodiment includes a first package component including a first integrated circuit die and a first encapsulant at least partially surrounding the first integrated circuit die. The device also includes a redistribution structure on the first encapsulant and coupled to the first integrated circuit die. The device also includes a first thermal module coupled to the first integrated circuit die. The device also includes a second package component bonded to the first package component, the second package component including a power module attached to the first package component, the power module including active devices. The device also includes a second thermal module coupled to the power module. The device also includes a mechanical brace extending from a top surface of the second thermal module to a bottom surface of the first thermal module, the mechanical brace physically contacting the first thermal module and the second thermal module.

Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.

Abstract: The present disclosure provides a semiconductor structure including a vertical inductor. The semiconductor structure includes a first semiconductor substrate, a first conductive layer, a first magnetic layer, and a second magnetic layer. The first semiconductor substrate has a top surface, and the first conductive layer is vertically inserted into the first semiconductor substrate from the top surface of the first semiconductor substrate. The first magnetic layer is disposed in the first semiconductor substrate and surrounds the first conductive layer. The second magnetic layer is disposed over the first conductive layer and the first magnetic layer.

Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.