Patents by Inventor Chi-Hui Lai

Chi-Hui Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210066242
    Abstract: A package includes a package substrate, an interposer over and bonded to the package substrate, a first wafer over and bonding to the interposer, and a second wafer over and bonding to the first wafer. The first wafer has independent passive device dies therein. The second wafer has active device dies therein.
    Type: Application
    Filed: March 2, 2020
    Publication date: March 4, 2021
    Inventors: Chen-Hua Yu, Kuo Lung Pan, Shu-Rong Chun, Chi-Hui Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu
  • Publication number: 20210057302
    Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.
    Type: Application
    Filed: November 9, 2020
    Publication date: February 25, 2021
    Inventors: Tsung-Hsien Chiang, Yu-Chih Huang, Ting-Ting Kuo, Chih-Hsuan Tai, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20210027777
    Abstract: The invention provides a method to generate a personalized phonation monitoring module, and a system thereof. The method comprises collecting, by a recorder, a voice from an individual; converting, by a processor, the voice to a voice signal; extracting a signal feature from the voice signal; providing a trained individualized speech recognition neural network; generating, by applying the signal feature to the trained speech recognition neural network, a voice marker; and generating a personal phonation recognition module including the voice marker. The invention is capable of providing real-time, delayed, or summary feedback of phonation when the analysis result is higher or lower than the pre-set value.
    Type: Application
    Filed: July 24, 2020
    Publication date: January 28, 2021
    Inventors: CHI-TE WANG, YING-HUI LAI
  • Publication number: 20210020538
    Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Chen, Hao-Yi Tsai, Kuo-Lung Pan, Tin-Hao Kuo, Po-Yuan Teng, Chi-Hui Lai
  • Publication number: 20210005586
    Abstract: A semiconductor structure includes a semiconductor package and a connector. The semiconductor package includes a die and a redistribution structure. The redistribution structure is disposed over the die, and includes a plurality of conductive patterns stacking on one another and electrically connected to the die. The connector is disposed on the redistribution structure, and includes a connecting element. The connecting element penetrates the conductive patterns and is electrically connected to the die.
    Type: Application
    Filed: September 17, 2020
    Publication date: January 7, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hui Lai, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Tin-Hao Kuo
  • Patent number: 10861841
    Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Cheng Tseng, Yu-Chih Huang, Chih-Hsuan Tai, Ting-Ting Kuo, Chi-Hui Lai, Ban-Li Wu, Chiahung Liu, Hao-Yi Tsai
  • Publication number: 20200381362
    Abstract: A semiconductor package includes a first wafer, a second wafer, and an interconnect. The first wafer includes a first die, a first encapsulating material encapsulating the first die, and a first redistribution structure disposed over the first die and the first encapsulating material. The second wafer includes a second die, a second encapsulating material encapsulating the second die, and a second redistribution structure disposed over the second die and the second encapsulating material, wherein the second redistribution structure faces the first redistribution structure. The interconnect is disposed between the first wafer and the second wafer and electrically connecting the first redistribution structure and the second redistribution structure, wherein the interconnect includes a substrate and a plurality of through vias extending through the substrate for connecting the first redistribution structure and the second redistribution structure.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Cheng Tseng, Hao-Yi Tsai, Tin-Hao Kuo, Chia-Hung Liu, Chi-Hui Lai
  • Patent number: 10840227
    Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chi-Hui Lai, Ban-Li Wu, Ying-Cheng Tseng, Ting-Ting Kuo, Chih-Hsuan Tai, Hao-Yi Tsai, Chuei-Tang Wang, Chung-Shi Liu, Chen-Hua Yu, Chiahung Liu
  • Patent number: 10832985
    Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Hsien Chiang, Yu-Chih Huang, Ting-Ting Kuo, Chih-Hsuan Tai, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10790269
    Abstract: Semiconductor devices and semiconductor structures are disclosed. One of the semiconductor device includes a semiconductor package and a connector. The semiconductor package includes at least one die in a die region, an encapsulant in a periphery region aside the die region and a redistribution structure in the die region and the periphery region. The encapsulant encapsulates the at least one die. The redistribution structure is electrically connected to the die. The connector is disposed on the redistribution structure in the periphery region. The connector includes a plurality of connecting elements, wherein the connector is electrically connected to the redistribution structure through the plurality of connecting elements.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hui Lai, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Tin-Hao Kuo
  • Publication number: 20200294916
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes semiconductor dies, an encapsulant and a redistribution structure. The semiconductor dies are disposed side by side. Each semiconductor die has an active surface, a backside surface, and an inner side surface connecting the active surface and the backside surface. The encapsulant wraps the semiconductor dies and exposes the active surfaces of the semiconductor dies. The redistribution structure is disposed on the encapsulant and the active surfaces of the semiconductor dies. The inner side surfaces of most adjacent semiconductor dies face each other. The redistribution structure establishes single-ended connections between most adjacent semiconductor dies by crossing over the facing inner side surfaces of the most adjacent semiconductor dies.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chia Lai, Chi-Hui Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Kuo-Chung Yee, Chen-Hua Yu
  • Publication number: 20200279837
    Abstract: A semiconductor package includes a semiconductor device including a first UBM structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips bonded to one of the multiple first conductive strips or one of the multiple second conductive strips.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Chih-Hsuan Tai, Chi-Hui Lai, Ying-Cheng Tseng, Ban-Li Wu, Ting-Ting Kuo, Yu-Chih Huang, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20200251407
    Abstract: A device includes a package. The package includes a plurality of dies, an encapsulant encapsulating the plurality of dies, and a redistribution structure over the plurality of dies and the encapsulant. The device further includes first sockets bonded to a top surface of the redistribution structure and a rigid/flexible substrate bonded to the top surface of the redistribution structure. The rigid/flexible substrate includes a first rigid portion, a second rigid portion, and a flexible portion interposed between the first rigid portion and the second rigid portion. The device further includes second sockets bonded to the first rigid portion of the rigid/flexible substrate and connector modules bonded to the second rigid portion of the rigid/flexible substrate.
    Type: Application
    Filed: November 1, 2019
    Publication date: August 6, 2020
    Inventors: Shu-Rong Chun, Tin-Hao Kuo, Chi-Hui Lai, Kuo Lung Pan, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20200243494
    Abstract: Semiconductor devices and semiconductor structures are disclosed. One of the semiconductor device includes a semiconductor package and a connector. The semiconductor package includes at least one die in a die region, an encapsulant in a periphery region aside the die region and a redistribution structure in the die region and the periphery region. The encapsulant encapsulates the at least one die. The redistribution structure is electrically connected to the die. The connector is disposed on the redistribution structure in the periphery region. The connector includes a plurality of connecting elements, wherein the connector is electrically connected to the redistribution structure through the plurality of connecting elements.
    Type: Application
    Filed: January 29, 2019
    Publication date: July 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Hui Lai, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Tin-Hao Kuo
  • Publication number: 20200243429
    Abstract: In an embodiment, a device includes: a package component including: a first integrated circuit die; an encapsulant at least partially surrounding the first integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure physically and electrically coupling the first integrated circuit die; a first module socket attached to the redistribution structure; an interposer attached to the redistribution structure adjacent the first module socket, the outermost extent of the interposer extending beyond the outermost extent of the redistribution structure; and an external connector attached to the interposer.
    Type: Application
    Filed: August 1, 2019
    Publication date: July 30, 2020
    Inventors: Chi-Hui Lai, Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20200212018
    Abstract: A packaged semiconductor device including an integrated passive device-containing package component disposed between a power module and an integrated circuit-containing package and a method of forming the same are disclosed. In an embodiment, a device includes a first package component including a first integrated circuit die; a first encapsulant at least partially surrounding the first integrated circuit die; and a redistribution structure on the first encapsulant and coupled to the first integrated circuit die; a second package component bonded to the first package component, the second package component including an integrated passive device; and a second encapsulant at least partially surrounding the integrated passive device; and a power module attached to the first package component through the second package component.
    Type: Application
    Filed: October 1, 2019
    Publication date: July 2, 2020
    Inventors: Chi-Hui Lai, Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10658348
    Abstract: A semiconductor package includes a semiconductor device including a first UBM structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips bonded to one of the multiple first conductive strips or one of the multiple second conductive strips.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Chi-Hui Lai, Ying-Cheng Tseng, Ban-Li Wu, Ting-Ting Kuo, Yu-Chih Huang, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20200105738
    Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.
    Type: Application
    Filed: December 10, 2018
    Publication date: April 2, 2020
    Inventors: Ying-Cheng Tseng, Yu-Chih Huang, Chih-Hsuan Tai, Ting-Ting Kuo, Chi-Hui Lai, Ban-Li Wu, Chiahung Liu, Hao-Yi Tsai
  • Publication number: 20200105638
    Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.
    Type: Application
    Filed: February 4, 2019
    Publication date: April 2, 2020
    Inventors: Tsung-Hsien Chiang, Yu-Chih Huang, Ting-Ting Kuo, Chih-Hsuan Tai, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20200105730
    Abstract: A semiconductor package includes a semiconductor device including a first UBM structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips bonded to one of the multiple first conductive strips or one of the multiple second conductive strips.
    Type: Application
    Filed: December 10, 2018
    Publication date: April 2, 2020
    Inventors: Chih-Hsuan Tai, Chi-Hui Lai, Ying-Cheng Tseng, Ban-Li Wu, Ting-Ting Kuo, Yu-Chih Huang, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu