Patents by Inventor Chi-Hui Lin
Chi-Hui Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145632Abstract: A micro light emitting device includes an epitaxial structure, a conductive layer, and a first insulating layer. The epitaxial structure has a first surface and a second surface opposite to the first surface, and includes a first semiconductor layer, an active layer and a second semiconductor layer that are arranged in such order in a direction from the first surface to the second surface. The conductive layer is formed on a surface of the first semiconductor layer away from the active layer. The first insulating layer is formed on the surface of the first semiconductor layer away from the active layer, and exposes at least a part of the conductive layer.Type: ApplicationFiled: October 23, 2023Publication date: May 2, 2024Inventors: Ming-Chun TSENG, Shaohua HUANG, Hongwei WANG, Kang-Wei PENG, Su-Hui LIN, Xiaomeng LI, Chi-Ming TSAI, Chung-Ying CHANG
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Patent number: 11964201Abstract: A modular pneumatic somatosensory device comprises a main body, a plurality of airbags, a plurality of inflating modules and a control module. The airbags are detachably disposed at different positions of the main body, and at least a part of the airbags have different sizes. The inflating modules are detachably disposed on the main body, and each inflating module is correspondingly connected with at least one of the airbags. The control module is detachably disposed on the main body and is electrically connected with the inflating modules. The control module controls the inflating modules to inflate the corresponding airbags according to a control signal.Type: GrantFiled: February 3, 2022Date of Patent: April 23, 2024Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Jen-Hui Chuang, June-Hao Hou, Chi-Li Cheng, Han-Ting Lin
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Patent number: 11927940Abstract: A management method for a cutting tool of a machine tool is provided. A user host imports a graphical data of a workpiece and a cutting tool database into CAM, and a user may select cutting tools to establish a complete machining process. T codes are replaced with electronic tags. Before executing a machine code comprising the electronic tags, the machine tool re-scans the cutting tools assembled at a tool turret and updates cutting tool arrangement information to ensure that the tool turret is equipped with the cutting tools used in the machining process. When the machine tool stores the electronic tags, a ready message is displayed for reminding an operator. When the electronic tags are not stored, the current storage location of a cutting tool lacked in the machining process or a warning message is displayed at the operation interface for reminding the operator.Type: GrantFiled: March 31, 2023Date of Patent: March 12, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chao-Chuang Mai, Chin-Hui Chen, Chi-Hsiang Lin, Zi-Chiao Lin
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Publication number: 20140072479Abstract: The present invention discloses a delivery equipment for the solid precursor particles, which is applied to the deposition of thin film. The delivery equipment for the solid precursor particles mainly comprises a container, a feeding material inlet, a feeding material tube, a feeding gas inlet, a feeding gas tube, and an output. A plurality of solid precursor particles are stored in the carrier liquid of the container, and then heated to be vapor, removed through the output of the container. The solid precursor particles are prepared by sublimation or grounding and uniformly dispersed in the carrier liquid. The disclosed delivery equipment for the solid precursor particles can reduce the required heating temperature, increase the thermal stability, prolong the used life time, and then increase the using efficiency of the precursors.Type: ApplicationFiled: November 5, 2012Publication date: March 13, 2014Applicant: NANMAT TECHNOLOGY CO., LTD.Inventors: Cheng-Jye CHU, Yu-Chen ZHENG, Chih-Hung CHEN, Chi-Hui LIN, Meng-Chung CHEN
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Patent number: 7476929Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.Type: GrantFiled: November 9, 2005Date of Patent: January 13, 2009Assignee: Nanya Technology CorporationInventors: Ching-Nan Hsiao, Chi-Hui Lin, Ying-Cheng Chuang
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Patent number: 7323743Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.Type: GrantFiled: November 22, 2006Date of Patent: January 29, 2008Assignee: Nanya Technology CorporationInventors: Ying-Cheng Chuang, Chung-Lin Huang, Chi-Hui Lin
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Patent number: 7205603Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.Type: GrantFiled: January 23, 2004Date of Patent: April 17, 2007Assignee: Nanya Technology CorporationInventors: Ying-Cheng Chuang, Chung-Lin Huang, Chi-Hui Lin
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Publication number: 20070063260Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.Type: ApplicationFiled: November 22, 2006Publication date: March 22, 2007Inventors: Ying-Cheng Chuang, Chung-Lin Huang, Chi-Hui Lin
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Patent number: 7135731Abstract: A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.Type: GrantFiled: December 10, 2003Date of Patent: November 14, 2006Assignee: Nanya Technology Corp.Inventors: Ching-Nan Hsiao, Ying-Cheng Chuang, Chi-Hui Lin
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Patent number: 7129537Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device is disposed in a cell trench within a substrate to achieve higher integration of memory cells.Type: GrantFiled: March 9, 2005Date of Patent: October 31, 2006Assignee: Nanya Technology CorporationInventor: Chi-Hui Lin
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Patent number: 7056792Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate to achieve higher integration of memory cells.Type: GrantFiled: April 6, 2004Date of Patent: June 6, 2006Assignee: Nanya Technology CorporationInventor: Chi-Hui Lin
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Patent number: 7022573Abstract: A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source conducting layer, a gate dielectric layer formed on a sidewall of the trench, a conducting spacer covering the gate dielectric layer as a floating gate, an inter-gate dielectric layer covering the conducting spacer, and a control gate conducting layer filled in the trench.Type: GrantFiled: July 2, 2004Date of Patent: April 4, 2006Assignee: Nanya Technology CorporationInventors: Ching-Nan Hsiao, Ying-Cheng Chuang, Chi-Hui Lin
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Publication number: 20060063339Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.Type: ApplicationFiled: November 9, 2005Publication date: March 23, 2006Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Ching-Nan Hsiao, Chi-Hui Lin, Ying-Cheng Chuang
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Patent number: 7005698Abstract: A split gate flash memory cell. The memory cell includes a substrate, a conductive line, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive line is disposed in a lower portion of the trench of the substrate. The source region is formed in the substrate adjacent to an upper portion of the conductive line having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate adjacent to the conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate adjacent to the first conductive layer.Type: GrantFiled: September 23, 2003Date of Patent: February 28, 2006Assignee: Nanya Technology CorporationInventors: Chi-Hui Lin, Jeng-Ping Lin, Pei-Ing Lee, Jih-Chang Lien
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Patent number: 7005701Abstract: A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.Type: GrantFiled: December 13, 2002Date of Patent: February 28, 2006Assignee: Nanya Technology CorporationInventors: Ching-Nan Hsiao, Chi-Hui Lin, Chung-Lin Huang, Ying-Cheng Chuang
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Patent number: 6998313Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device is disposed in a cell trench within a substrate to achieve higher integration of memory cells.Type: GrantFiled: December 11, 2003Date of Patent: February 14, 2006Assignee: Nanya Technology CorporationInventor: Chi-Hui Lin
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Patent number: 6995061Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.Type: GrantFiled: February 18, 2004Date of Patent: February 7, 2006Assignee: Nanya Technology CorporationInventors: Ching-Nan Hsiao, Chi-Hui Lin, Ying-Cheng Chuang
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Patent number: 6921694Abstract: A method for fabricating a floating gate with multiple tips. A semiconductor substrate is provided, on which an insulating layer and a patterned hard mask layer are sequentially formed. The patterned hard mask layer has an opening to expose the surface of the semiconductor substrate. A conducting layer is conformally formed on the patterned hard mask layer, and the opening is filled with the conducting layer. The conducting layer is planarized to expose the surface of the patterned hard mask layer. The conducting layer is thermally oxidized to form an oxide layer, and the patterned hard mask layer is removed.Type: GrantFiled: May 19, 2003Date of Patent: July 26, 2005Assignee: Nanya Technology CorporationInventors: Ying-Cheng Chuang, Chung-Lin Huang, Chi-Hui Lin
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Publication number: 20050156233Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device is disposed in a cell trench within a substrate to achieve higher integration of memory cells.Type: ApplicationFiled: March 9, 2005Publication date: July 21, 2005Applicant: NANYA TECHNOLOGY CORPORATIONInventor: Chi-Hui Lin
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Patent number: 6916715Abstract: A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.Type: GrantFiled: October 27, 2003Date of Patent: July 12, 2005Assignee: Nanya Technology CorporationInventors: Ching-Nan Hsiao, Chi-Hui Lin, Chung-Lin Huang, Ying-Cheng Chuang