Abstract: A memory architecture of display device comprises a memory cell array having a plurality of memory cells arranged as a plurality of cell rows and a plurality of cell columns, and a data latch circuit having a plurality of latch units for storing a plurality of bits; wherein the number of the latch units is equal to that of the memory cells in each cell row, such that each bit stored in the data latch circuit can be written to each memory cell of one cell row at one time. The present invention also provides a memory writing method.

Abstract: A liquid crystal display (LCD) device connectable to a power source includes a substrate, a panel including an array of thin film transistors provided on the substrate, and a first integrated circuit (IC). The first IC includes a timing controller for providing control signals and video signals, a source driver for receiving the control signals and video signals and driving the panel, and a common voltage circuit for providing a common voltage to the panel.