Abstract: Some embodiments relate to a pixel array, including: a substrate including a first side and a second side opposite the first side; a plurality of photodetectors in the substrate, the plurality of photodetectors symmetrically disposed around a middle axis between the plurality of photodetectors, where the middle axis is perpendicular to the first side and the second side; a first doped region at the middle axis between the plurality of photodetectors and on the first side of the substrate; a frontside deep trench isolation (DTI) structure on the first side of the substrate and extending directly between photodetectors of the plurality of photodetectors; and a backside DTI structure on the second side of the substrate and spacing the frontside DTI structure from the middle axis.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a plurality of photodetectors in a substrate. The substrate comprises a first surface opposite a second surface. An outer isolation structure is disposed in the substrate and laterally surrounds the plurality of photodetectors. The outer isolation structure has a first height. An inner isolation structure is spaced between sidewalls of the outer isolation structure. The inner isolation structure is disposed between adjacent photodetectors in the plurality of photodetectors. The outer isolation structure and the inner isolation structure respectively extend from the second surface toward the first surface. The inner isolation structure comprises a second height less than the first height.

Abstract: Some embodiments relate to A deep trench isolation (DTI) structure, including: a DTI core extending into a substrate; a first film surrounding the DTI core and having a first material with a first conduction band at a first band energy; a second film between the first film and the DTI core, the second film having a second material with a second conduction band at a second band energy less than the first band energy; and a third film between the second film and the DTI core, the third film having a third material with a third conduction band at a third band energy greater than the second band energy.

Abstract: A system and a method for automatically adjusting a beam direction of a reflector are provided. The system includes: a reflector for reflecting, refracting, or transmitting incident waves of network signals to a specified area; a database, storing optimized setting combinations for specified areas that include an altitude of the reflector and angles thereof with respect to the specified area, making signals of the specified area have maximum intensity; a communication module, receiving a trigger signal; a computing and processing module, retrieving from the optimized setting combination for the specified area according to the area name of the trigger signal; and a control module, adjusting the altitude and angles of the reflector according to the optimized setting combination. The disclosure can automatically detect a specified area needing network service and automatically adjust the reflector for signal intensity enhancement.

Abstract: A method is described. The method includes obtaining a relationship between a thickness of a contamination layer formed on a mask and an amount of compensation energy to remove the contamination layer, obtaining a first thickness of a first contamination layer formed on the mask from a thickness measuring device, and applying first compensation energy calculated from the relationship to a light directed to the mask.

Abstract: An image sensor includes a plurality of pixels. At least one pixel includes first and second photosensitive regions, first and second transfer gate transistors and a floating diffusion region. The first and second photosensitive regions are located within a substrate and adjacent to each other. The first and second photosensitive regions are different in at least one of doping depth and conductivity type. The first and second photosensitive regions are overlapped with an opening of a grid structure disposed on a backside surface of the substrate. The first and second transfer gate transistors are disposed on a frontside surface of the substrate and respectively overlapped with the first and second photosensitive regions. The floating diffusion region is located within the substrate and shared between the first and second photosensitive regions.

Abstract: Some embodiments relate to an integrated circuit (IC) device including a first IC die and a second IC die. The first IC die includes first and second conductive structures at a first surface of the first IC die, and the first and second conductive structures are laterally separated by a first dielectric structure. The second IC die includes third and fourth conductive structures at a first surface of the second IC die, and the third and fourth conductive structures are laterally separated by a second dielectric structure. The first surface of the first IC die faces the first surface of the second IC die such that the first conductive structure vertically contacts the third conductive structure to form a first capacitor electrode, and the second conductive structure vertically contacts the fourth conductive structure to form a second capacitor electrode. The first and second capacitor electrodes form a capacitor.

Abstract: In some implementations, one or more semiconductor processing tools may form a triple-stacked polysilicon structure on a substrate of a semiconductor device. The one or more semiconductor processing tools may form one or more polysilicon-based devices on the substrate of the semiconductor device, wherein the triple-stacked polysilicon structure has a first height that is greater than one or more second heights of the one or more polysilicon-based devices. The one or more semiconductor processing tools may perform a chemical-mechanical polishing (CMP) operation on the semiconductor device, wherein performing the CMP operation comprises using the triple-stacked polysilicon structure as a stop layer for the CMP operation.

Abstract: The present invention discloses an automatic signal deployer, a signal deployment system, an automatic signal path deployment method, and a behavior control signal generation method of a deployment agent. The signal deployment system includes an automatic signal deployer, a deployment agent and a base station. The deployment agent receives signal quality data, generates a behavior control signal according to the signal quality data, and sends out the behavior control signal to the automatic signal deployer. The automatic signal deployer receives the behavior control signal and a source signal coming from the base station, performs deployment according to the behavior control signal, whereby the automatic signal deployer can transmit the source signal toward a signal path allocation direction and complete automatic deployment of signal paths.

Abstract: An electronic device is provided. The electronic device includes a housing, a panel, and a circuit board. The panel is disposed on the housing. The circuit board is electrically connected to the panel. The circuit board has a first ground terminal and a second ground terminal. The first ground terminal and the second ground terminal have no electrical connection path within the circuit board. The first ground terminal is electrically connected to the housing through a first conductive medium, and the second ground terminal is electrically connected to the housing through a second conductive medium.

Abstract: A restriction device is adapted to be mounted to a nail gun that has a barrel device and that accommodates a plurality of nails. Each nail has a nail head and a nail shaft. The restriction device includes a restriction member that has first and second obstruction portions. The restriction member is adapted to be movable between an obstruction position and a release position. When the restriction member is in the obstruction position, the first obstruction portion is adapted to be slotted between the nail shaft of one of the plurality of nails and the nail shaft of an adjacent one of the plurality of nails, and the second obstruction portion is adapted to abut against the nail head of the one of the plurality of nails or to abut the nail shaft of the adjacent one of the plurality of nails against the barrel device.

Abstract: A method comprises cleaning a surface of a reticle by irradiating the surface of the reticle in a first exposure device for a predetermined irradiation time. A layout pattern of the reticle is projected onto a photo resist layer of a wafer in a second exposure device by an EUV radiation. The photo resist layer is developed to generate a photo resist pattern on the wafer. A surface of the wafer is imaged to generate an image of the photo resist pattern on the wafer. The generated image of the photo resist pattern is analyzed to determine critical dimension uniformity (CDU) of the photo resist pattern. The predetermined irradiation time is adjusted until the determined CDU satisfies a predetermined criterion.

Abstract: A method includes emitting, by a first portion of an optical inspection instrument, a radiation toward a supporting surface of a chuck, wherein the chuck is configured for fixing a semiconductor workpiece on the supporting surface, and the optical inspection instrument faces the supporting surface; receiving, by a second portion of the optical inspection instrument, a reflection of the radiation reflected from the chuck; analyzing the reflection of the radiation; determining whether a particle is present on the supporting surface of the chuck based on the analyzing the reflection of the radiation; and removing the particle by using a cleaning tool comprising an exhaust duct.

Abstract: A magnetic shield reduces external noise in a chamber including a target and at least one electromagnet for copper physical vapor deposition (PVD). The shield may have a thickness in a range from approximately 0.1 mm to approximately 10 mm to provide sufficient protection from radio frequency and other electromagnetic signals. As a result, copper atoms in the chamber undergo less re-direction from external noise. Additionally, even when hardware failure occurs during PVD (e.g., an electromagnet malfunctions, a wafer stage is not level, and/or a flow optimizer induces too much shift, among other examples), the copper atoms are less susceptible to small re-directions from external noise. As a result, back end of line (BEOL) and/or middle end of line (MEOL) conductive structures are formed in a more uniform manner, which increases conductivity and improves lifetime of an electronic device including the BEOL and/or MEOL conductive structures.

Abstract: Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.

Abstract: A pulley and string arrangement structure of a bow contains a bow body, an arm assembly, two pulleys, a string fixer, a main string, two first auxiliary strings, and two second auxiliary strings. The bow body includes an arrow-receiving portion. The arm assembly is mounted on the bow body and extends from the bow body. A respective one pulley includes a main string layer, a first and second retraction units, a first and second defining portions, a first and second expansion units, and a first and second locating portions. The main string layer has a guide grove and a positioning portion. The first and second retraction units include a first and second guiding slots. The first and second expansion units include a first and second conduct slots. A center of the arm assembly and the main string layer has a virtual datum plane.

Abstract: A method for manufacturing a golf club head with sole textures comprises steps of providing and bending a crude rod made of a metallic material, a first forging process for forming a uniaxial tilting blank of a head body via a first forging die, a second forging process for forming a biaxial tilting blank of the head body via a second forging die, and a third forging process for forming a club head with sole textures via a third die. Compared with machining grooves to a sole of the club head, the method is time efficient and cost effective.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first integrated chip (IC) tier and a second IC tier. The second IC tier comprises a second plurality of conductors within a second insulating structure disposed on the second semiconductor body. A conductive pad is electrically coupled to the second plurality of conductors and has a conductive surface available to a side of the second semiconductor body facing away from the first semiconductor body. The IC first tier contacts the second IC tier along a bonding interface including one or more conductive regions and one or more insulating regions. The one or more conductive regions laterally outside of a bottom surface of the conductive pad.

Abstract: The present disclosure relates to a multi-dimensional image sensor integrated chip (IC) structure. The multi-dimensional image sensor IC structure includes a plurality of image sensing elements disposed within a plurality of pixel regions arranged in a pixel array of a first integrated chip (IC) tier. The plurality of pixel regions include a plurality of active pixel regions and one or more dummy pixel regions. A plurality of pixel support devices are disposed on a second substrate within a second IC tier that is bonded to the first IC tier. A plurality of logic devices are disposed within a third IC tier that is bonded to the second IC tier. A through substrate via (TSV) extends vertically through the second substrate laterally outside of the plurality of pixel support devices and directly below the pixel array.

Abstract: Various embodiments of the present disclosure are directed to a stacked complementary metal-oxide semiconductor (CMOS) image sensor. A first integrated circuit (IC) chip and a second IC chip are vertically stacked. A pixel sensor spans the first and second IC chips. The pixel sensor comprises a first transfer transistor and a photodetector that are at the first IC chip, and further comprises a source-follower transistor, a transistor capacitor, and a second transfer transistor that are at the second IC chip. The transistor capacitor and the second transfer transistor are electrically coupled in series from a source/drain region of the first transfer transistor to a gate electrode of the source-follower transistor.