Abstract: Various embodiments of the present disclosure are directed to a stacked complementary metal-oxide semiconductor (CMOS) image sensor. A first integrated circuit (IC) chip and a second IC chip are vertically stacked. A pixel sensor spans the first and second IC chips. The pixel sensor comprises a first transfer transistor and a photodetector that are at the first IC chip, and further comprises a source-follower transistor, a transistor capacitor, and a second transfer transistor that are at the second IC chip. The transistor capacitor and the second transfer transistor are electrically coupled in series from a source/drain region of the first transfer transistor to a gate electrode of the source-follower transistor.

Abstract: The present disclosure relates to a multi-dimensional image sensor integrated chip (IC) structure. The multi-dimensional image sensor IC structure includes a plurality of image sensing elements disposed within a plurality of pixel regions arranged in a pixel array of a first integrated chip (IC) tier. The plurality of pixel regions include a plurality of active pixel regions and one or more dummy pixel regions. A plurality of pixel support devices are disposed on a second substrate within a second IC tier that is bonded to the first IC tier. A plurality of logic devices are disposed within a third IC tier that is bonded to the second IC tier. A through substrate via (TSV) extends vertically through the second substrate laterally outside of the plurality of pixel support devices and directly below the pixel array.

Abstract: A method comprises cleaning a surface of a reticle by irradiating the surface of the reticle in a first exposure device for a predetermined irradiation time. A layout pattern of the reticle is projected onto a photo resist layer of a wafer in a second exposure device by an EUV radiation. The photo resist layer is developed to generate a photo resist pattern on the wafer. A surface of the wafer is imaged to generate an image of the photo resist pattern on the wafer. The generated image of the photo resist pattern is analyzed to determine critical dimension uniformity (CDU) of the photo resist pattern. The predetermined irradiation time is adjusted until the determined CDU satisfies a predetermined criterion.

Abstract: A cold plate comprises a plurality of fins. The individual fins have an opening, and the openings collectively define a first channel through the plurality of fins. During operation of an integrated circuit component attached to the cold plate, coolant is pumped through the cold plate. The coolant flows in a first direction through the first channel and then in a second through second channels located between the fins. The first direction is substantially orthogonal to the second direction. The first channel can comprise a tube that has openings that direct coolant to flow into the second channels. The first channel is located close to the base plate of the cold plate so that there is a high degree of heat transfer between an integrated circuit component attached to the cold plate and coolant flowing through the cold plate.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a first integrated circuit (IC) die stacked with a second IC die. The first IC die includes a plurality of photodetectors disposed within a first substrate. The second IC die includes a plurality of pixel transistors and a semiconductor capacitor disposed on a second substrate. The semiconductor capacitor includes a first capacitor electrode, a capacitor dielectric layer, and a doped capacitor region. The first capacitor electrode overlies the second substrate and comprises a protrusion disposed in the second substrate. The capacitor dielectric layer is disposed between the first capacitor electrode and the second substrate. The doped capacitor region is disposed within the second substrate and underlies the first capacitor electrode. The plurality of photodetectors, the plurality of pixel transistors, and the semiconductor capacitor define a pixel.

Abstract: A p-type doping region around an isolation structure provides additional electrical isolation between pixel sensors of a pixel array. As a result, current leakage from a floating node of one pixel sensor into another is reduced. Therefore, dark current is reduced, and performance of the pixel array is improved. Additionally, pixel noise caused by electrons trapped in the isolation structure may be reduced.

Abstract: A method for manufacturing an iron golf club head has acts of providing a head body made of a metallic material, providing at least one weight insert made of a high-specific-gravity metallic material, forming engagement features at either the head body or the weight insert, and assembling and forging. Therefore, different metallic materials are integrally combined by forging to form the golf club head with a precise appearance. The head body and the weight insert are joined without gaps to enhance hitting performance and reduce noises upon striking. Flexibility of gravity center position is increased for achieving preferred requirements of lowing center of gravity and deepening the center of gravity.

Abstract: A semiconductor image-sensing structure includes a reflective grid and a reflective shield disposed over a substrate. The reflective grid is disposed in a first region, and the reflective shield is disposed in a second region separated from the first region. A thickness of the reflective shield is greater than a thickness of the reflective grid.

Abstract: A semiconductor device includes a substrate having a front side and a back side opposite to each other. A plurality of photodetectors is disposed in the substrate within a pixel region. An isolation structure is disposed within the pixel region and between the photodetectors. The isolation structure includes a back side isolation structure extending from the back side of the substrate to a position in the substrate. A conductive plug structure is disposed in the substrate within a periphery region. A conductive cap is disposed on the back side of the substrate and extends from the pixel region to the periphery region and electrically connects the back side isolation structure to the conductive plug structure. A conductive contact lands on the conductive plug structure, and is electrically connected to the back side isolation structure through the conductive plug structure and the conductive cap.

Abstract: A method according to the present disclosure includes providing a first workpiece that includes a first substrate and a first interconnect structure, providing a second workpiece that includes a second substrate, a second interconnect structure, and a through via extending through a portion of the second substrate and a portion of the second interconnect structure, forming a first bonding layer on the first interconnect structure, forming a second bonding layer on the second interconnect structure, bonding the second workpiece to the first workpiece by directly bonding the second bonding layer to the first bonding layer, thinning the second substrate, forming a protective film over the thinned second substrate, forming a backside via opening through the protective film and the thinned second substrate to expose the through via, and forming a backside through via in the backside via opening to physically couple to the through via.

Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.

Abstract: A foldable electronic device includes a first body having an end and a first inclined surface, a second body having a second inclined surface, and a hinge module. The end includes an accommodating area. A virtual shaft line exists between sides of the first inclined surface and the second inclined surface that are closest to each other. The second body rotates relative to the first body through the virtual shaft line. The hinge module includes a first bracket adjacent to the first inclined surface, connected to the first body, and located in the accommodating area, a second bracket adjacent to the second inclined surface and connected to the second body, and a third bracket including a first end and a second end. The first bracket is connected to the first end through a first torsion assembly. The second bracket is connected to the second end through a second torsion assembly.

Abstract: In some implementations, one or more semiconductor processing tools may form a triple-stacked polysilicon structure on a substrate of a semiconductor device. The one or more semiconductor processing tools may form one or more polysilicon-based devices on the substrate of the semiconductor device, wherein the triple-stacked polysilicon structure has a first height that is greater than one or more second heights of the one or more polysilicon-based devices. The one or more semiconductor processing tools may perform a chemical-mechanical polishing (CMP) operation on the semiconductor device, wherein performing the CMP operation comprises using the triple-stacked polysilicon structure as a stop layer for the CMP operation.

Abstract: A data storage device includes a memory device and a memory controller. In response to a write command received from a host device, the memory controller performs a write operation to write predetermined data into the memory device. In the write operation, the memory controller selects one from multiple superblocks as a first target superblock of the write operation and sequentially writes the portions of the predetermined data into the pages of the first target superblock in a cyclic manner among memory dies according to an order of plane indices. Each memory die includes at least a first plane and a second plane. In the write operation corresponding to the predetermined data, corresponding write operations performed on a first page on the first plane of all memory dies are earlier than corresponding write operations performed on a first page on the second plane of all memory dies.

Abstract: Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.

Abstract: An electronic package module and a method for fabrication of the same are provided. The method includes providing an electronic component assembly and a circuit substrate. The electronic component assembly includes two electronic components and a conductive structure. The electronic components are connected to each other through a conductive adhesive material, while the electronic components are connected to the conductive structure through another conductive adhesive material. A soldering material is formed on the circuit substrate, and the electronic component assembly is disposed on the soldering material. The melting points of the conductive adhesive materials are higher than the melting point of the soldering material. As a result, the conductive adhesive materials are prevented from failure during the soldering process, and thus the process yield is improved.

Abstract: A polysilicon well is formed at a cross-road portion between a plurality of pixel sensors in a pixel sensor array. Moreover, the underlying oxide layer between the polysilicon well and a semiconductor layer of the pixel sensor array may be thinner than other areas of the oxide layer. The polysilicon well and the thinner oxide layer may reduce the likelihood of and/or the magnitude of lateral etching that occurs during etching of the semiconductor layer to form recesses in which a BDTI structure of the pixel sensor array is formed. Moreover, the bottom of the BDTI structure being surrounded by the polysilicon well enables a voltage bias to be applied to the BDTI structure through the polysilicon well to passivate damage that might have occurred to the semiconductor layer around the bottom of the BDTI structure.

Abstract: A cap nailer includes a machine body, a muzzle, a magazine, a cap feeding device, and a nail striking device. The muzzle is connected to the machine body and extends along a first axis. The magazine is connected to the muzzle, and extends in an extending direction of a second axis. The cap feeding device includes a cap cartridge that is juxtaposed with the magazine, and a cap rail that is connected to the cap cartridge and that has a third axis. The cap cartridge is adapted for accommodating a plurality of caps. The third axis and the first axis define an intersection point that is spaced apart from the muzzle. The cap rail is adapted for guiding the caps to move to the intersection point, and cooperates with the magazine to define a first included angle therebetween. The first included angle ranges from 15 degrees to 25 degrees.

Abstract: A gas mixing method to enhance plasma includes: providing a reaction chamber; wherein the reaction chamber includes an accommodating space and the reaction chamber includes a top opening connected to the accommodating space; providing an adapter plate, and fixing the adapter plate to the reaction chamber to be arranged corresponding to the top opening; wherein the adapter plate further includes a window area communicating both sides of the adapter plate; providing a target disposed on top of the adapter plate to seal the top opening; premixing a plasma gas and an auxiliary gas into a gas mixture, and introducing the gas mixture into the accommodating space; and providing a biasing field to the accommodating space.

Abstract: A particle prevention method in chamber includes providing a shielding ring, wherein the shielding ring includes a first side wall, a second side wall, and a bottom, the second side wall is parallel to the first side wall, and the bottom is connected to the first side wall, and the second side wall to form an annular groove area; connecting the first side wall to the reaction chamber with the first side wall extending toward an upper portion of a accommodating space of a reaction chamber; fixing a first deflector plate to the first side wall, wherein the first deflector plate extends obliquely toward the bottom, and the first deflector plate is located above the aperture; and fixing a second deflector plate to the second side wall, wherein the second deflector plate is located above the first deflector plate, and the second deflector plate extends obliquely toward the bottom.