Patents by Inventor Chi-Hung Kao
Chi-Hung Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7774516Abstract: A communicating system suitable for a repeater and communicating method thereof are described. The communicating system comprises a receiving unit, a delay module, a transmitting unit and a control unit. The receiving unit transmits a first signal based on a KB/MS input signal. The delay module is coupled to the receiving unit and delays the first signal from the receiving unit in order to generate a second signal. The second signal has a first phase difference in comparison with the first signal. The transmitting unit is coupled to the delay module and the control unit. The transmitting unit transmits a KB/MS output signal based on the second signal while the control unit controls the transmitting unit via a control signal.Type: GrantFiled: November 8, 2006Date of Patent: August 10, 2010Assignee: Aten International Co., Ltd.Inventors: Chih-tao Hsieh, Fu-Chin Shen, Chi-Hung Kao
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Publication number: 20090046478Abstract: An optical film includes a substrate and at least one pyramid-like structure. The pyramid-like structure is disposed on one surface of the substrate and has a base, a first face, a second face and a third face. The first, second and third faces are connected together and disposed along the base.Type: ApplicationFiled: January 29, 2008Publication date: February 19, 2009Inventors: Horng-Jou Wang, Chi-Hung Kao, Huang-kun Chen
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Publication number: 20080179615Abstract: A light-emitting diode (LED) device includes a substrate, at least one LED element and an optical modulation structure. The LED element is disposed on the substrate and generates a light beam. The optical modulation structure is disposed at one side of the LED element for adjusting a shape of an optical field of the light beam and an intensity distribution of the optical field. The optical modulation structure is formed with a plurality of stepped protrusions.Type: ApplicationFiled: December 13, 2007Publication date: July 31, 2008Inventors: Chi-Hung KAO, Horng-Jou Wang, Huang-Kun Chen
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Publication number: 20080179614Abstract: A light-emitting diode (LED) package includes a thermal-conducting substrate, a LED element, a package body, and an optical modulation device. The LED element is formed on the thermal-conducting substrate. The package body is formed on the LED element and the thermal-conducting substrate, and the optical modulation device is disposed on a light outputting surface of the package body and has a plurality of stepped protrusions for adjusting a shape of an optical field of the light beam. The optical modulation device and the package body can be two separate components and be connected together, or the optical modulation device and the package body can be integrally formed as a single piece when they are made. In addition, a manufacturing method of the LED package is also disclosed.Type: ApplicationFiled: November 27, 2007Publication date: July 31, 2008Inventors: Horng-Jou Wang, Chi-Hung Kao, Huang-Kun Chen
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Publication number: 20080122784Abstract: A communicating system suitable for a repeater and communicating method thereof are described. The communicating system comprises a receiving unit, a delay module, a transmitting unit and a control unit. The receiving unit transmits a first signal based on a KB/MS input signal. The delay module is coupled to the receiving unit and delays the first signal from the receiving unit in order to generate a second signal. The second signal has a first phase difference in comparison with the first signal. The transmitting unit is coupled to the delay module and the control unit. The transmitting unit transmits a KB/MS output signal based on the second signal while the control unit controls the transmitting unit via a control signal.Type: ApplicationFiled: November 8, 2006Publication date: May 29, 2008Applicant: Aten International Co., Ltd.Inventors: Chih-Tao Hsieh, Fu-Chin Shen, Chi-Hung Kao
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Patent number: 7358817Abstract: A linearized bias circuit with adaptation resolves the problem happening to the power amplifier with conventional bias circuit that the DC and AC characteristics of the power amplifier shift or even deteriorate due to a temperature variation. The linearized bias circuit with adaptation has a reference voltage source, a first voltage source, a first resistor, a second resistor, a first NPN transistor, a second NPN transistor, and a third NPN transistor. The present invention has the characteristics of bias current temperature compensation, gain and phase compensations to achieve high linearity for the conventional power amplifier and reducing the DC consumption power. At the same time, the quantity of the required elements and layout area in the present invention are small so that the design complexity can be reduced for improving yield, reducing IC layout area, and reducing cost.Type: GrantFiled: April 5, 2006Date of Patent: April 15, 2008Assignee: RichWave Technology Corp.Inventors: Chi-Hung Kao, Chih-Wei Chen, Cheng-Min Lin, Yun-Shan Chang, Shyh-Chyi Wong
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Publication number: 20070200858Abstract: A KVM switch has a switching device, a first computer video interface, a second computer video interface, an image processing unit, and at least one console video interface. The switching device is arranged to select a first computing device and a second computing device from the computing devices. The first computer video interface is arranged to receive a first image from the first computing device, and the second computer video interface is arranged to receive a second image from the second computing device. The image processing unit is arranged to compose the first image and the second image to be a synthesized image. The console video interface is arranged to output one of the first image, the second image and the synthesized image to the set of user interface devices.Type: ApplicationFiled: February 28, 2006Publication date: August 30, 2007Inventors: Chih-Iao Hsieh, Chi-Hung Kao, Chin-Chou Lin
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Publication number: 20060226911Abstract: A linearized bias circuit with adaptation resolves the problem happening to the power amplifier with conventional bias circuit that the DC and AC characteristics of the power amplifier shift or even deteriorate due to a temperature variation. The linearized bias circuit with adaptation has a reference voltage source, a first voltage source, a first resistor, a second resistor, a first NPN transistor, a second NPN transistor, and a third NPN transistor. The present invention has the characteristics of bias current temperature compensation, gain and phase compensations to achieve high linearity for the conventional power amplifier and reducing the DC consumption power. At the same time, the quantity of the required elements and layout area in the present invention are small so that the design complexity can be reduced for improving yield, reducing IC layout area, and reducing cost.Type: ApplicationFiled: April 5, 2006Publication date: October 12, 2006Inventors: Chi-Hung Kao, Chih-Wei Chen, Cheng-Min Lin, Yun-Shan Chang, Shyh-Chyi Wong
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Patent number: 6734493Abstract: Within both a lateral double diffused metal oxide semiconductor (LDMOS) device, and a method for fabrication thereof, there is formed a buried layer of polarity equivalent with a well region within which is formed a drain region. The buried layer is formed laterally aligned with respect to the well region, and separated therefrom by a portion of an epitaxial layer. The lateral double diffused metal oxide semiconductor (LDMOS) device exhibits enhanced electrical performance.Type: GrantFiled: February 8, 2002Date of Patent: May 11, 2004Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Hui Chen, Chi-Hung Kao, Jeng Gong, Kuo-Hsu Huang, Meng-Chi Wu, Jia-Rong Yu
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Publication number: 20030151088Abstract: Within both a lateral double diffused metal oxide semiconductor (LDMOS) device, and a method for fabrication thereof, there is formed a buried layer of polarity equivalent with a well region within which is formed a drain region. The buried layer is formed laterally aligned with respect to the well region, and separated therefrom by a portion of an epitaxial layer. The lateral double diffused metal oxide semiconductor (LDMOS) device exhibits enhanced electrical performance.Type: ApplicationFiled: February 8, 2002Publication date: August 14, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Hui Chen, Chi-Hung Kao, Jeng Gong, Kuo--Hsu Huang, Meng-Chi Wu, Jia-Rong Yu
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Patent number: 6541325Abstract: The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so that the thickness of the dielectric layer of the capacitor device decreased relative to a specific ion concentration. Accordingly, the capacitor device formed therein has a high capacitance and good performance.Type: GrantFiled: May 1, 2002Date of Patent: April 1, 2003Assignee: Windbond Electronics CorporationInventors: Chih-Mu Huang, Chuan-Jane Chao, Chi-Hung Kao
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Patent number: 6468870Abstract: A method of manufacturing a LDHOS transistor having a dielectric block under the gate electrode. A high voltage well, low voltage well (LV PW), and field oxide regions having bird beaks are provided in a substrate and overlay the high voltage well and the low voltage well. In a key step, a dielectric block is formed over the bird beaks of the field oxide regions. A gate is formed over the dielectric block. After this the LDMOS device is completed. The invention's dielectric block covers the bird's beaks of the field oxide regions and enhances the e-field tolerance. The invention's e-field enhancement dielectric block relieves the e-field near the bird's beak, thus increasing the breakdown voltage of the transistor.Type: GrantFiled: December 26, 2000Date of Patent: October 22, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chi-Hung Kao, Shih-Hui Chen, Tsung-Yi Huang, Jeng Gong, Kuo-Shu Huang
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Publication number: 20020123191Abstract: The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so that the thickness of the dielectric layer of the capacitor device decreased relative to a specific ion concentration. Accordingly, the capacitor device formed therein has a high capacitance and good performance.Type: ApplicationFiled: May 1, 2002Publication date: September 5, 2002Applicant: Winbond Electronics Corporation, a Taiwan corporationInventors: Chih-Mu Huang, Chuan-Jane Chao, Chi-Hung Kao
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Publication number: 20020070806Abstract: An ATG MOSFET is constructed of a plurality of ATG MOSFET elements each including a gate region. One of a source and drain region of each ATG MOSFET element is shared in common with an adjacent one of the ATG MOSFET elements. The plurality of ATG MOSFET elements are connected in parallel to provide a desired driving current capacity and reduced effective driving capacitance. The ATG MOSFET is implemented in a high frequency RF amplifier.Type: ApplicationFiled: June 30, 1999Publication date: June 13, 2002Inventors: SHYH-CHYI WONG, CHI-HUNG KAO
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Patent number: 6392285Abstract: The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so that the thickness of the dielectric layer of the capacitor device decreased relative to a specific ion concentration. Accordingly, the capacitor device formed therein has a high capacitance and good performance.Type: GrantFiled: December 14, 1999Date of Patent: May 21, 2002Assignee: Winbond Electronics CorporationInventors: Chih-Mu Huang, Chuan-Jane Chao, Chi-Hung Kao
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Patent number: 6292393Abstract: A method is used to fully extract coupling coefficients of a flash memory cell by a GIDL manner. The flash memory cell is composed of a substrate, a drain region, source region, a control gate and a floating gate. The method keeps the source voltage Vs and the substrate voltage Vb fixed. The drain voltage Vd and the control gate voltage are varied. Then, measuring a GIDL current obtains a first coefficient ratio of the drain coupling coefficient ad to the gate coupling &agr;cg, that is, &agr;d/&agr;cg. Similarly, keeping the drain voltage Vd and the substrate voltage Vb fixed and varying the source voltage Vs and the control gate voltage Vcg, a second coefficient ratio of the source coupling coefficient &agr;s to the gate coupling coefficient &agr;cg, that is, &agr;s/&agr;cg.Type: GrantFiled: March 20, 2000Date of Patent: September 18, 2001Assignee: Winbond Electronics Corp.Inventors: Jung-Yu Tsai, Chih-Mu Huang, Chi-Hung Kao, Chuan-Jane Chao