Patents by Inventor Chi-Hwa Tsang
Chi-Hwa Tsang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869894Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.Type: GrantFiled: July 13, 2022Date of Patent: January 9, 2024Assignee: Intel CorporationInventors: Aaron D. Lilak, Anh Phan, Patrick Morrow, Willy Rachmady, Gilbert Dewey, Jessica M. Torres, Kimin Jun, Tristan A. Tronic, Christopher J. Jezewski, Hui Jae Yoo, Robert S. Chau, Chi-Hwa Tsang
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Publication number: 20220344376Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.Type: ApplicationFiled: July 13, 2022Publication date: October 27, 2022Applicant: Intel CorporationInventors: Aaron D. Lilak, Anh Phan, Patrick Morrow, Willy Rachmady, Gilbert Dewey, Jessica M. Torres, Kimin Jun, Tristan A. Tronic, Christopher J. Jezewski, Hui Jae Yoo, Robert S. Chau, Chi-Hwa Tsang
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Patent number: 11430814Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.Type: GrantFiled: March 5, 2018Date of Patent: August 30, 2022Assignee: Intel CorporationInventors: Aaron D. Lilak, Anh Phan, Patrick Morrow, Willy Rachmady, Gilbert Dewey, Jessica M. Torres, Kimin Jun, Tristan A. Tronic, Christopher J. Jezewski, Hui Jae Yoo, Robert S. Chau, Chi-Hwa Tsang
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Patent number: 11417567Abstract: Conductive cap-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer above a substrate. Each of the conductive lines is recessed relative to an uppermost surface of the ILD layer. A plurality of conductive caps is on corresponding ones of the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the plurality of conductive caps and on the uppermost surface of the ILD layer. The hardmask layer includes a first hardmask component on and aligned with the plurality of conductive caps, and a second hardmask component on an aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a conductive cap of one of the plurality of conductive lines.Type: GrantFiled: December 23, 2016Date of Patent: August 16, 2022Assignee: Intel CorporationInventors: Florian Gstrein, Eungnak Han, Rami Hourani, Ruth A. Brain, Paul A. Nyhus, Manish Chandhok, Charles H. Wallace, Chi-Hwa Tsang
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Publication number: 20200395386Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.Type: ApplicationFiled: March 5, 2018Publication date: December 17, 2020Applicant: Intel CorporationInventors: Aaron D. Lilak, Anh Phan, Patrick Morrow, Willy Rachmady, Gilbert Dewey, Jessica M. Torres, Kimin Jun, Tristan A. Tronic, Christopher J. Jezewski, Hui Jae Yoo, Robert S. Chau, Chi-Hwa Tsang
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Publication number: 20190363008Abstract: Conductive cap-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer above a substrate. Each of the conductive lines is recessed relative to an uppermost surface of the ILD layer. A plurality of conductive caps is on corresponding ones of the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the plurality of conductive caps and on the uppermost surface of the ILD layer. The hardmask layer includes a first hardmask component on and aligned with the plurality of conductive caps, and a second hardmask component on an aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a conductive cap of one of the plurality of conductive lines.Type: ApplicationFiled: December 23, 2016Publication date: November 28, 2019Inventors: Florian GSTREIN, Eungnak HAN, Rami HOURANI, Ruth A. BRAIN, Paul A. NYHUS, Manish CHANDHOK, Charles H. WALLACE, Chi-Hwa TSANG
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Publication number: 20150371949Abstract: Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature, which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites.Type: ApplicationFiled: August 31, 2015Publication date: December 24, 2015Applicant: INTEL CORPORATIONInventors: Daniel J. Zierath, Shaestagir Chowdhury, Chi-Hwa Tsang
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Patent number: 9123706Abstract: Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature, which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites.Type: GrantFiled: December 21, 2011Date of Patent: September 1, 2015Assignee: INTEL CORPORATIONInventors: Daniel J. Zierath, Shaestagir Chowdhury, Chi-Hwa Tsang
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Publication number: 20130270703Abstract: Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites.Type: ApplicationFiled: December 21, 2011Publication date: October 17, 2013Inventors: Daniel J. Zierath, Shaestagir Chowdhury, Chi-Hwa Tsang
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Publication number: 20110147831Abstract: An exemplary embodiment of a method for forming a gate for a planar-type or a finFET-type transistor comprises forming a gate trench that includes an interior surface. A first work-function metal is formed on the interior surface of the gate trench, and a low-resistivity material is deposited on the first work-function metal using a chemical vapor deposition (CVD) technique, or an atomic layer deposition (ALD) technique, or combinations thereof. Another exemplary embodiment provides that a second work-function metal is formed on the first work-function metal, and then the low-resistivity material is deposited on the first work-function metal using a chemical vapor deposition (CVD) technique, or an atomic layer deposition (ALD) technique, or combinations thereof.Type: ApplicationFiled: December 23, 2009Publication date: June 23, 2011Inventors: Joseph M. Steigerwald, Jack Hwang, Chi-Hwa Tsang, Michael Ollinger, Mengcheng Lu
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Patent number: 7622382Abstract: Methods of fabricating an interconnect utilizing an electroless deposition technique, which fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, and electrolessly depositing a conductive material within the opening. A dual-function barrier layer is formed within the opening. The dual-function barrier layer is capable of acting as a diffusion barrier layer and a nucleation surface for a conductive material. An electrolessly deposited conductive material is formed immediately above the dual-function barrier layer. An ultra-thin seed layer may be formed immediately on top of the barrier layer prior to the electrolessly deposited conductive material being formed thereon.Type: GrantFiled: March 29, 2006Date of Patent: November 24, 2009Assignee: Intel CorporationInventors: Shaestagir Chowdhury, Chi-Hwa Tsang
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Patent number: 7432200Abstract: Methods of fabricating an interconnect utilizing an electroless deposition technique, which fundamentally consists of providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, and electrolessly depositing a conductive material within the opening. Various processing steps and structures may be utilized in the fabrication of the interconnect, which may include but is not limited to forming barrier layers, utilizing seed materials, utilizing activation materials, and treating the dielectric material to be receptive to electroless deposition.Type: GrantFiled: December 15, 2005Date of Patent: October 7, 2008Assignee: Intel CorporationInventors: Shaestagir Chowdhury, Chi-Hwa Tsang
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Publication number: 20070232044Abstract: Methods of fabricating an interconnect utilizing an electroless deposition technique, which fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, and electrolessly depositing a conductive material within the opening. A dual-function barrier layer is formed within the opening. The dual-function barrier layer is capable of acting as a diffusion barrier layer and a nucleation surface for a conductive material. An electrolessly deposited conductive material is formed immediately above the dual-function barrier layer. An ultra-thin seed layer may be formed immediately on top of the barrier layer prior to the electrolessly deposited conductive material being formed thereon.Type: ApplicationFiled: March 29, 2006Publication date: October 4, 2007Inventors: Shaestagir Chowdhury, Chi-Hwa Tsang
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Publication number: 20070141826Abstract: Methods of fabricating an interconnect utilizing an electroless deposition technique, which fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, and electrolessly depositing a conductive material within the opening. Various processing steps and structures may be utilized in the fabrication of the interconnect, which may include but is not limited to forming barrier layers, utilizing seed materials, utilizing activation materials, and treating the dielectric material to be receptive to electroless deposition.Type: ApplicationFiled: December 15, 2005Publication date: June 21, 2007Inventors: Shaestagir Chowdhury, Chi-Hwa Tsang
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Patent number: 7070687Abstract: Apparatus and method for treating a surface of a substrate for electrolytic or electroless plating of metals in integrated circuit manufacturing. In one embodiment the method includes forming a barrier layer on a substrate. A metal-seed layer is then formed on the barrier layer. The method continues by performing in situ surface treatment of the metal-seed layer to form a passivation layer on the metal-seed layer. In another embodiment of a method of this invention, a substrate is provided into an electroplating tool chamber. The substrate has a barrier layer formed thereon, a metal seed layer formed on the barrier layer and a passivation layer formed over the metal seed layer. The method continues by annealing the substrate in forming gas to reduce the passivation layer. A conductive material is deposited on the substrate using an electrolytic plating or electroless plating process.Type: GrantFiled: August 14, 2001Date of Patent: July 4, 2006Assignee: Intel CorporationInventors: Vinay B. Chikarmane, Chi-Hwa Tsang
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Publication number: 20040235390Abstract: A method and system for reclaiming virgin test wafers by polishing a very thin layer from the wafer surface, applying a low down force between the wafer and the pad, with a dilute, low basic slurry. By polishing only a few hundred Angstroms of silicon from the wafer surface, a virgin test wafer may be repeatedly reclaimed and reused for periodic defect monitoring.Type: ApplicationFiled: April 12, 2004Publication date: November 25, 2004Inventors: Hossein Rojhantalab, Chi-Hwa Tsang, Sean J. King
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Patent number: 6761625Abstract: A method and system for reclaiming virgin test wafers by polishing a very thin layer from the wafer surface, applying a low down force between the wafer and the pad, with a dilute, low basic slurry. By polishing only a few hundred Angstroms of silicon from the wafer surface, a virgin test wafer may be repeatedly reclaimed and reused for periodic defect monitoring.Type: GrantFiled: May 20, 2003Date of Patent: July 13, 2004Assignee: Intel CorporationInventors: Hossein Rojhantalab, Chi-Hwa Tsang, Sean W King
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Publication number: 20030034251Abstract: Apparatus and method for treating a surface of a substrate for electrolytic or electroless plating of metals in integrated circuit manufacturing. In one embodiment the method includes forming a barrier layer on a substrate. A metal-seed layer is then formed on the barrier layer. The method continues by performing in situ surface treatment of the metal-seed layer to form a passivation layer on the metal-seed layer.Type: ApplicationFiled: August 14, 2001Publication date: February 20, 2003Inventors: Vinay B. Chikarmane, Chi-Hwa Tsang
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Patent number: 5358891Abstract: A method of forming and refilling a trench in a substrate. First a trench is formed in the substrate. The trench is then refilled with a conformal material. Next, a recess is etched into the top portion of the refilled trench. The recess is then refilled with a second material until the refilled recess and substrate are substantially planar.Type: GrantFiled: June 29, 1993Date of Patent: October 25, 1994Assignee: Intel CorporationInventors: Chi-Hwa Tsang, Kerry L. Spurgin, Deborah A. Parsons, William L. Hargrove, Ganesan Radhakrishnan
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Patent number: 5262279Abstract: A dry process for stripping photoresist from a polyimide surface formed on a substrate is described. The present invention is practiced after a polyimide layer has been etched. Prior to etching, the polyimide surface is masked with photoresist which is then patterned. The polyimide is etched in exposed regions, for example to form vias to expose contacts located beneath the polyimide layer. The present invention then strips the photoresist in a single wafer downstream plasma etcher in a plasma comprising oxygen radicals. The polyimide is subjected to a short preheat before introduction of the oxygen plasma, and is also heated during the stripping process. The strip proceeds until an endpoint is detected. The endpoint is detected by a change in the spectral emission of the plasma which occurs due to a decrease in the amount of CH.sub.3 radicals present in the system when the polyimide surface is reached. A short timed over-etch is then employed to ensure complete removal of the photoresist.Type: GrantFiled: September 9, 1992Date of Patent: November 16, 1993Assignee: Intel CorporationInventors: Chi-Hwa Tsang, Peter K. Charvat, Robert M. Guptill