Patents by Inventor Chi-Jen Yang
Chi-Jen Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12211793Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.Type: GrantFiled: July 18, 2022Date of Patent: January 28, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ni-Wan Fan, Ting-Wei Chiang, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Lipen Yuan, Chi-Yu Lu
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Patent number: 12170202Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: GrantFiled: January 2, 2023Date of Patent: December 17, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
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Patent number: 12166126Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.Type: GrantFiled: June 23, 2022Date of Patent: December 10, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chieh Wang, Sheng-Wei Yeh, Yueh-Ching Pai, Chi-Jen Yang
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Publication number: 20240363350Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: ApplicationFiled: July 8, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
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Patent number: 12111339Abstract: A state detection circuit for detecting whether a state of an input node is floating, grounded, or electrically connected to an external voltage includes: a unidirectional device circuit and a determination circuit. The unidirectional device circuit electrically conducts a test node to a detection node unidirectionally. The detection node is coupled to the input node. The test node, the unidirectional device circuit, the detection node and the input node form a current path. The determination circuit determines a state of the input node according to a voltage level of the detection node. Within a detection stage, the state detection circuit provides a test voltage at the test node. A voltage of the detection node is determined by the input node, the test voltage, and a characteristic of the unidirectional device circuit.Type: GrantFiled: October 28, 2022Date of Patent: October 8, 2024Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Chun-Jen Yu, Hsuan-Kai Wang, Chi-Jen Yang, Hsien-Chih She
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Publication number: 20240305186Abstract: A switching converter includes: a power stage circuit which includes at least one switch to switch an inductor to convert an input power to an output power; a first loop control circuit configured to switch the at least one switch by a peak current mode according to a first feedback signal related to the output power and an inductor current of the inductor in a first control mode; and a second loop control circuit configured to control the at least one switch to switch with a switching period according to a second feedback signal in a second control mode. If the power stage circuit operates in DCM during consecutively more than a predetermined number of the switching periods, the switching converter enters the first control mode. A portion of sub-circuits of the second loop control circuit are turned off to reduce power consumption in the first control mode.Type: ApplicationFiled: October 16, 2023Publication date: September 12, 2024Inventors: Chun-Jen Yu, Chi-Jen Yang
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Patent number: 11752800Abstract: A non-pneumatic tire includes a tread layer and a spoke layer including an inner cylinder and several spoke assemblies. The tread layer is annular and has a maximum outer diameter of the non-pneumatic tire and is adapted to be in contact with a ground. The spoke assemblies extend in a radial direction of the non-pneumatic tire and are arranged around an axial core of the non-pneumatic tire. An end of each spoke assembly is connected to the inner cylinder, and another end thereof is connected to the tread layer. Each spoke assembly includes a straight spoke, a bending spoke, and a connecting rib. Each bending spoke includes a first segment and a second segment, which are not connected in a straight line. Each connecting rib has a first end connected to the straight spoke and a second end opposite to the first end and connected to the bending spoke. When the non-pneumatic tire bears a weight and is squeezed, the spoke assemblies do not get in contact with one another.Type: GrantFiled: August 20, 2020Date of Patent: September 12, 2023Assignee: KENDA RUBBER IND. CO., LTD.Inventors: Chi-Jen Yang, Min-Fan Huang, Jia-Yi Jiang
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Publication number: 20230198473Abstract: An amplifier circuit having low parasitic pole effect includes a preamplifier, an output transistor and a buffer circuit. The buffer circuit generates a driving signal to control the output transistor according to a preamplification signal generated by the preamplifier. The buffer circuit includes: a buffer input transistor generating the driving signal, wherein an input impedance at its control end is less than that of the output transistor; a low output impedance circuit having an output impedance which is less than an inverting output impedance of the buffer input transistor; an amplification transistor generating an amplification signal at its inverting output; and an amplification stage circuit amplifying the amplification signal by an amplification ratio, so that an equivalent output impedance at a non-inverting output of the buffer input transistor is less than or equal to a product of the reciprocal of an intrinsic output impedance thereof and an amplification ratio.Type: ApplicationFiled: November 17, 2022Publication date: June 22, 2023Inventors: Chun-Jen Yu, Ssu-Wei Huang, Hsuan-Kai Wang, Chi-Jen Yang, Hsien-Chih She
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Publication number: 20230160935Abstract: A state detection circuit for detecting whether a state of an input node is floating, grounded, or electrically connected to an external voltage includes: a unidirectional device circuit and a determination circuit. The unidirectional device circuit electrically conducts a test node to a detection node unidirectionally. The detection node is coupled to the input node. The test node, the unidirectional device circuit, the detection node and the input node form a current path. The determination circuit determines a state of the input node according to a voltage level of the detection node. Within a detection stage, the state detection circuit provides a test voltage at the test node. A voltage of the detection node is determined by the input node, the test voltage, and a characteristic of the unidirectional device circuit.Type: ApplicationFiled: October 28, 2022Publication date: May 25, 2023Inventors: Chun-Jen Yu, Hsuan-Kai Wang, Chi-Jen Yang, Hsien-Chih She
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Publication number: 20230141521Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: ApplicationFiled: January 2, 2023Publication date: May 11, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yu LIN, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
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Patent number: 11545363Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: GrantFiled: December 21, 2020Date of Patent: January 3, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
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Publication number: 20220336653Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.Type: ApplicationFiled: June 23, 2022Publication date: October 20, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chieh Wang, Sheng-Wei Yeh, Yueh-Ching Pai, Chi-Jen Yang
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Patent number: 11411112Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.Type: GrantFiled: May 31, 2020Date of Patent: August 9, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chieh Wang, Sheng-Wei Yeh, Yueh-Ching Pai, Chi-Jen Yang
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Publication number: 20210129587Abstract: A non-pneumatic tire includes a tread layer and a spoke layer including an inner cylinder and several spoke assemblies. The tread layer is annular and has a maximum outer diameter of the non-pneumatic tire and is adapted to be in contact with a ground. The spoke assemblies extend in a radial direction of the non-pneumatic tire and are arranged around an axial core of the non-pneumatic tire. An end of each spoke assembly is connected to the inner cylinder, and another end thereof is connected to the tread layer. Each spoke assembly includes a straight spoke, a bending spoke, and a connecting rib. Each bending spoke includes a first segment and a second segment, which are not connected in a straight line. Each connecting rib has a first end connected to the straight spoke and a second end opposite to the first end and connected to the bending spoke. When the non-pneumatic tire bears a weight and is squeezed, the spoke assemblies do not get in contact with one another.Type: ApplicationFiled: August 20, 2020Publication date: May 6, 2021Applicant: KENDA RUBBER IND. CO., LTD.Inventors: CHI-JEN YANG, MIN-FAN HUANG, JIA-YI JIANG
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Publication number: 20210111027Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
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Publication number: 20210036147Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.Type: ApplicationFiled: May 31, 2020Publication date: February 4, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Chieh Wang, Sheng-Wei Yeh, Yueh-Ching Pai, Chi-Jen Yang
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Patent number: 10872769Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: GrantFiled: December 30, 2019Date of Patent: December 22, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
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Publication number: 20200135471Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: ApplicationFiled: December 30, 2019Publication date: April 30, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
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Patent number: 10535523Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.Type: GrantFiled: August 30, 2018Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yu Lin, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
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Patent number: 8796562Abstract: A combiner box includes a combiner module and an electrical connector unit disposed in a casing. The combiner module includes an insulating board, and plural first and second input electrodes disposed on opposite surfaces of the insulating board along a first direction and corresponding respectively to plural first and second input sockets of the casing. The second input sockets are disposed below and alternatingly arranged with the first input sockets along the first direction. The electrical connector unit includes plural first and second input terminals disposed in the first and second input sockets and electrically connected to the first and second input electrodes, respectively.Type: GrantFiled: April 10, 2012Date of Patent: August 5, 2014Inventor: Chi-Jen Yang