Patents by Inventor Chi Jin
Chi Jin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11948545Abstract: A sound control device in a vehicle and control method thereof may include obtaining energy per unit time of an audio signal corresponding to a preset low frequency band, calculating an allowable reference value based on a difference between a magnitude of energy per unit time of the audio signal and a magnitude of a preset maximum allowable input of a speaker, monitoring whether a magnitude of energy per unit time of a noise control signal for eliminating noise in the vehicle exceeds the allowable reference value, and adjusting a magnitude of the noise control signal when the magnitude of energy per unit time of the noise control signal exceeds the allowable reference value.Type: GrantFiled: October 19, 2022Date of Patent: April 2, 2024Assignees: HYUNDAI MOTOR COMPANY, KIA CORPORATIONInventors: Jung Keun You, Jong Won Lee, Kaang Dok Yee, Chi Sung Oh, Hyun Jin Song
-
Publication number: 20240107794Abstract: The present disclosure relates to an organic electroluminescent device. The organic electroluminescent device according to the present disclosure includes a deuterated organic electroluminescent material, so it can exhibit a low driving voltage and high luminous efficiency.Type: ApplicationFiled: August 29, 2023Publication date: March 28, 2024Inventors: Su-Hyun LEE, Soo-Yong LEE, Chi-Sik KIM, HaeYeon KIM, Yoo-Jin DOH, SeungAe KIM, Mi-Ja LEE
-
Publication number: 20240097174Abstract: The present disclosure relates to a secondary battery manufacturing system having a multi-packaging unit, in which multiple packaging units of a secondary battery manufacturing facility are provided and a transfer box on which an electrode assembly is accommodated is transferred to each packaging unit by a transfer unit, wherein the secondary battery manufacturing system includes: an electrode supply unit equipped with a plurality of stacking devices for supplying an electrode assembly in which a plurality of battery cells are stacked; a tab-welding unit; at least one packaging unit; at least one temporary buffer; and a transfer unit.Type: ApplicationFiled: September 14, 2023Publication date: March 21, 2024Inventors: Yong Uk SHIN, Sang Sik CHO, Dae Woon NAM, Dong Jin PARK, Jae Gyun CHOI, Chi Hong AN
-
Publication number: 20240099132Abstract: The present invention relates to an organic electroluminescent device comprising at least one light-emitting layer between an anode and a cathode, wherein the light-emitting layer comprises a host and a phosphorescent dopant; the host comprises plural host compounds; at least a first host compound of the plural host compounds has a structure of a nitrogen-containing heterocyclic linker bonded to a nitrogen atom of a carbazole of an indole-carbazole, indene-carbazole, benzofuran-carbazole, or benzothiophene-carbazole residue; and a second host compound has a carbazole-aryl-carbazole or carbazole-carbazole structure. According to the present invention, by using a specific multi-component host different from the conventional organic electroluminescent device, an organic electroluminescent device of significantly improved lifespan is provided.Type: ApplicationFiled: November 15, 2023Publication date: March 21, 2024Inventors: Kyoung-Jin PARK, Bitnari KIM, Yoo-Jin DOH, Hyun-Ju KANG, Young-Mook LIM, Su-Hyun LEE, Chi-Sik KIM
-
Publication number: 20240088027Abstract: An integrated circuit includes an inductor that includes a first set of conductors in at least a first metal layer, and a guard ring enclosing the inductor. The guard ring includes a first conductor extending in a first direction, a second conductor extending in a second direction, and a first set of staggered conductors coupled to a first end of the first conductor and a first end of the second conductor. The first set of staggered conductors includes a second set of conductors in a second metal layer, a third set of conductors in a third metal layer and a first set of vias coupling the second set of conductors with the third set of conductors. The third metal layer is above the second metal layer. All metal lines in the second metal layer that are part of the guard ring extend in the first direction.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: Chiao-Han LEE, Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Tzu-Jin YEH, Ying-Ta LU
-
Publication number: 20240090328Abstract: The present invention relates to a multi-component host material and an organic electroluminescent device comprising the same. By comprising a specific combination of the multi-component host compounds, the organic electroluminescent device according to the present invention can provide high luminous efficiency and excellent lifespan characteristics.Type: ApplicationFiled: October 26, 2023Publication date: March 14, 2024Inventors: Hee-Choon AHN, Young-Kwang KIM, Su-Hyun LEE, Ji-Song JUN, Seon-Woo LEE, Chi-Sik KIM, Kyoung-Jin PARK, Nam-Kyun KIM, Kyung-Hoon CHOI, Jae-Hoon SHIM, Young-Jun CHO, Kyung-Joo LEE
-
Patent number: 11926787Abstract: A well cementing method is described for improving cementing quality by controlling the hydration heat of cement slurry. By controlling the degree and/or rate of hydration heat release from cement slurry, the method improves the hydration heat release during formation of cement with curing of cement slurry, improves the binding quality between the cement and the interfaces, and in turn improves the cementing quality at the open hole section and/or the overlap section. The cementing method improves cementing quality of oil and gas wells and reduces the risk of annular pressure.Type: GrantFiled: April 21, 2020Date of Patent: March 12, 2024Assignees: PetroChina Company Limited, CNPC Engineering Technology R&D Company LimitedInventors: Shuoqiong Liu, Hua Zhang, Jianzhou Jin, Ming Xu, Yongjin Yu, Fengzhong Qi, Congfeng Qu, Hong Yue, Youcheng Zheng, Wei Li, Yong Ma, Youzhi Zheng, Zhao Huang, Jinping Yuan, Zhiwei Ding, Chongfeng Zhou, Chi Zhang, Zishuai Liu, Hongfei Ji, Yuchao Guo, Xiujian Xia, Yong Li, Jiyun Shen, Huiting Liu, Yusi Feng, Bin Lyu
-
Publication number: 20240079630Abstract: The present disclosure relates to a secondary battery manufacturing system in which a packaging unit of a secondary battery manufacturing facility are configured to have multiple packaging units, and having a multipackaging unit such that a transfer box in which an electrode assembly is seated is transferred to each of the packaging units by a transfer unit, and including an electrode supply unit having a plurality of stacking devices supplying an electrode assembly in which a plurality of battery cells are stacked, a tab welding unit, at least one packaging unit, at least one temporary buffer, and a transfer unit.Type: ApplicationFiled: September 1, 2023Publication date: March 7, 2024Inventors: Yong Uk SHIN, Sang Sik CHO, Dae Woon NAM, Dong Jin PARK, Jae Gyun CHOI, Chi Hong AN
-
Patent number: 11917907Abstract: The present disclosure relates to an organic electroluminescent device. The organic electroluminescent device of the present disclosure shows high luminous efficiency and good lifespan by comprising a specific combination of the plural kinds of host compounds and a specific hole transport compound.Type: GrantFiled: November 22, 2021Date of Patent: February 27, 2024Assignee: Rohm and Haas Electronic Materials Korea Ltd.Inventors: Kyoung-Jin Park, Tae-Jin Lee, Jae-Hoon Shim, Yoo Jin Doh, Hee-Choon Ahn, Young-Kwang Kim, Doo-Hyeon Moon, Jeong-Eun Yang, Su-Hyun Lee, Chi-Sik Kim, Ji-Song Jun
-
Patent number: 11688826Abstract: A light emitting device, a method of fabricating a light emitting device and a method of controlling light emission. The light emitting device includes a plasmonic structure. The plasmonic structure is configured to have a plurality of localized surface plasmon resonances. The light emitting device also includes a broadband light emitting layer having an emission spectrum substantially overlapping wavelengths of the localized surface plasmon resonances. A spacer layer is disposed between the plasmonic structure and the broadband light emitting layer. A color of light emitted by the broadband light emitting layer is tunable by the localized surface plasmon resonances of the plasmonic structure.Type: GrantFiled: June 5, 2018Date of Patent: June 27, 2023Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventors: Ee Jin Teo, Yi Shi, Chengyuan Yang, Qing Yang Steve Wu, Yin Thai Chan, Yang Xu, Chi Jin Darren Neo
-
Patent number: 11540162Abstract: The present invention discloses a wireless perception system energy and information transmission method of an unmanned aerial vehicle (UAV) swarm, comprising: building a wireless perception system architecture based on multi-UAV energy supply, wherein the system comprises a plurality of wireless powered sensors and a UAV swarm, and each sensor establishes connection with a UAV based on random access to realize network construction; designing energy and information transmission protocols in the swarm and between the swarm and the sensors, designing a joint optimization algorithm and solving optimal system configuration to obtain optimal transmission strategies. The present invention firstly proposes a joint optimization method of multi-network power allocation, time slot design and beam forming under the condition of multi-UAV autonomous collaborative energy supply, and also provides an efficient and reliable communication means for autonomous cooperative control of the UAV swarm.Type: GrantFiled: August 2, 2022Date of Patent: December 27, 2022Assignee: Jilin UniversityInventors: Fengye Hu, Chi Jin, Zhuang Ling, Zhi Mao, Ruozhou Lv, Wuliji Nashun, Zhijun Li
-
Publication number: 20220386162Abstract: The present invention discloses a wireless perception system energy and information transmission method of an unmanned aerial vehicle (UAV) swarm, comprising: building a wireless perception system architecture based on multi-UAV energy supply, wherein the system comprises a plurality of wireless powered sensors and a UAV swarm, and each sensor establishes connection with a UAV based on random access to realize network construction; designing energy and information transmission protocols in the swarm and between the swarm and the sensors, designing a joint optimization algorithm and solving optimal system configuration to obtain optimal transmission strategies. The present invention firstly proposes a joint optimization method of multi-network power allocation, time slot design and beam forming under the condition of multi-UAV autonomous collaborative energy supply, and also provides an efficient and reliable communication means for autonomous cooperative control of the UAV swarm.Type: ApplicationFiled: August 2, 2022Publication date: December 1, 2022Applicant: Jilin UniversityInventors: Fengye Hu, Chi Jin, Zhuang Ling, Zhi Mao, Ruozhou Lv, Wuliji Nashun, Zhijun Li
-
Publication number: 20200203560Abstract: A light emitting device, a method of fabricating a light emitting device and a method of controlling light emission. The light emitting device includes a plasmonic structure. The plasmonic structure is configured to have a plurality of localized surface plasmon resonances. The light emitting device also includes a broadband light emitting layer having an emission spectrum substantially overlapping wavelengths of the localized surface plasmon resonances. A spacer layer is disposed between the plasmonic structure and the broadband light emitting layer. A color of light emitted by the broadband light emitting layer is tunable by the localized surface plasmon resonances of the plasmonic structure.Type: ApplicationFiled: June 5, 2018Publication date: June 25, 2020Inventors: Ee Jin Teo, Yi Shi, Chengyuan Yang, Qing Yang Steve Wu, Yin Thai Chan, Yang Xu, Chi Jin Darren Neo
-
Publication number: 20180121814Abstract: Improvements in speed and reductions in computational resource expenditure are realized in the improved tuning of hyperparameters for machine learning processes. To ensure that the values selected for hyperparameters are tuned appropriately, but quickly, several rounds of optimization are performed, each with as many or more iterations of cross-validation than prior rounds; cutting short the analysis unpromising results to devote more time and resources in analyzing promising value sets. The results are used to build suggested sets of hyperparameter values for that round, which are also cross-validated and enable the tuning process to incorporate previous operations to improve its value sets. The most promising sets of hyperparameter values from each round are selected as the basis set for the next round until a final set of values for the hyperparameters is developed.Type: ApplicationFiled: March 8, 2017Publication date: May 3, 2018Applicant: Microsoft Technology Licensing, LLCInventors: Dong Yu, Chi Jin
-
Publication number: 20160329269Abstract: A chip package structure including a lead frame, a chip, a plurality of solder bumps, a solder resist layer and an encapsulant is provided. The lead frame has a plurality of inner leads. Each of the inner leads has an upper surface, a lower surface, two side surfaces opposite to each other and a bonding area on the upper surface. The chip is disposed on the lead frame and has an active surface. Each of the solder bumps connects the active surface and the bonding area of each of the inner leads. The solder resist layer is disposed on at least one of the lower surface or the two side surfaces of each of the inner leads. The encapsulant covers the lead frame, the chip, the solder bumps and the solder resist layer. A manufacturing method of the chip package structure is also provided.Type: ApplicationFiled: October 5, 2015Publication date: November 10, 2016Inventor: Chi-Jin Shih
-
Patent number: 9401318Abstract: A quad flat no-lead package includes an encapsulant, and a plurality of chip pads, a plurality of bond pads and a chip disposed in the encapsulant. Each chip pad is connected to at least one of the chip pads adjacent thereto by a first extending portion. The chip pads and the bond pads are arranged in an array. The chip pads are disposed at the center of the array and the bond pads are disposed around the chip pads. Each of the bond pads and at least one of the bond pads or one of the chip pads adjacent thereto each has a second extending portion formed therebetween and corresponding to each other. Every two of the second extending portions corresponding to each other are separated by a groove. The chip is mounted on a top surface of the chip pads and is electrically coupled to the bond pads.Type: GrantFiled: March 12, 2015Date of Patent: July 26, 2016Assignee: ChipMOS Technologies Inc.Inventor: Chi-Jin Shih
-
Patent number: 9318422Abstract: A flat no-lead package includes an encapsulating material, and a die pad, a chip, a plurality of first contact pads and a plurality of second contact pads disposed in the encapsulating material. The encapsulating material has a package bottom surface. The die pad has a plurality of die pad extensions extending from the edges thereof. The chip is mounted on the die pad. The first contact pads are disposed near the edges of the encapsulating material and electrically coupled to the chip. The second contact pads are located between the die pad and the first contact pads and electrically coupled to the chip. Each of the second contact pads have a second contact pad extension corresponding to one of the die pad extensions respectively. The bottom surfaces of the first contact pads, the second contact pads and the second contact pad extensions are exposed on the package bottom surface.Type: GrantFiled: February 11, 2015Date of Patent: April 19, 2016Assignee: ChipMOS Technologies Inc.Inventor: Chi-Jin Shih
-
Publication number: 20150303133Abstract: A flat no-lead package includes an encapsulating material, and a die pad, a chip, a plurality of first contact pads and a plurality of second contact pads disposed in the encapsulating material. The encapsulating material has a package bottom surface. The die pad has a plurality of die pad extensions extending from the edges thereof. The chip is mounted on the die pad. The first contact pads are disposed near the edges of the encapsulating material and electrically coupled to the chip. The second contact pads are located between the die pad and the first contact pads and electrically coupled to the chip. Each of the second contact pads have a second contact pad extension corresponding to one of the die pad extensions respectively.Type: ApplicationFiled: February 11, 2015Publication date: October 22, 2015Inventor: Chi-Jin SHIH
-
Publication number: 20150294925Abstract: A quad flat no-lead package includes an encapsulant, and a plurality of chip pads, a plurality of bond pads and a chip disposed in the encapsulant. Each chip pad is connected to at least one of the chip pads adjacent thereto by a first extending portion. The chip pads and the bond pads are arranged in an array. The chip pads are disposed at the center of the array and the bond pads are disposed around the chip pads. Each of the bond pads and at least one of the bond pads or one of the chip pads adjacent thereto each has a second extending portion formed therebetween and corresponding to each other. Every two of the second extending portions corresponding to each other are separated by a groove. The chip is mounted on a top surface of the chip pads and is electrically coupled to the bond pads.Type: ApplicationFiled: March 12, 2015Publication date: October 15, 2015Inventor: Chi-Jin SHIH
-
Publication number: 20150294957Abstract: A chip packaging structure includes an encapsulating material, plurality of first leads, plurality of second leads, a first chip, a second chip and an adhesion layer. The encapsulating material has a top package surface and a corresponding bottom package surface. Each first lead has a first inner lead portion and a first outer lead portion. The first chip is located on the first inner lead portion and electrically coupled to the first leads. Each second lead has a second inner lead portion and a second outer lead portion. The second chip is located on the second inner lead portion and electrically coupled to the second leads. The adhesion layer is located between the first leads and second leads so that the first leads and second leads are connected to each other.Type: ApplicationFiled: March 20, 2015Publication date: October 15, 2015Inventor: Chi-Jin SHIH