Abstract: A random-access memory has its bitcells arranged into a first pair of banks and a second pair of banks. The first pair of banks and second pair of banks are separated by a central controller that contains sense amplifiers and write drivers for the first pair of banks and for the second pair of banks.

Abstract: A circuit is provided with a selectively diode-connected head switch transistor. During a light-sleep mode, the head switch transistor is diode connected so that a power supply voltage passing through the diode-connected head switch transistor is reduced by a transistor threshold voltage drop. During an active mode, the diode connection is opened so that the head switch transistor passes a power supply voltage with virtually no voltage drop.

Abstract: A memory is provided that includes bitcell VDD boosting to increase a read margin. In some implementations, the positive boost for the bitcell VDD may be provided by a capacitor that is also used for negative boosting of a write driver.

Abstract: A memory is provided that includes bitcell VDD boosting to increase a read margin. In some implementations, the positive boost for the bitcell VDD may be provided by a capacitor that is also used for negative boosting of a write driver.

Abstract: Methods and apparatuses having an improved write assist scheme are presented. An apparatus includes a power supply node configured to provide power from a power supply to one memory cell to store data; a bitline configured to provide write data to the one memory cell in a write operation; and a discharge circuit configured to selectively discharge the power supply node to the bitline, based on the write data. A method to write into a memory cell with a write assist scheme includes providing power from a power supply to one memory cell via a power supply node, to store data; providing write data to the one memory cell via a bitline in a write operation; and discharging, selectively based on the write data, the power supply node to the bitline.

Abstract: A method for a memory subsystem redundancy with priority decoding is described. The method includes dynamically repairing a local input/output (IO) unit of a first memory subsystem bank based on a current redundancy fuse input pattern of the first memory subsystem bank. The method also includes concurrently generating a redundancy shift signal in each global IO based on the current redundancy fuse input pattern to shift the repaired local IO unit and lower order local IO units of the first memory subsystem bank relative to the repaired local IO unit.

Abstract: A method for a memory subsystem redundancy with priority decoding is described. The method includes dynamically repairing a local input/output (IO) unit of a first memory subsystem bank based on a current redundancy fuse input pattern of the first memory subsystem bank. The method also includes concurrently generating a redundancy shift signal in each global IO based on the current redundancy fuse input pattern to shift the repaired local IO unit and lower order local IO units of the first memory subsystem bank relative to the repaired local IO unit.

Abstract: Methods and apparatuses having an improved write assist scheme are presented. An apparatus includes a power supply node configured to provide power from a power supply to one memory cell to store data; a bitline configured to provide write data to the one memory cell in a write operation; and a discharge circuit configured to selectively discharge the power supply node to the bitline, based on the write data. A method to write into a memory cell with a write assist scheme includes providing power from a power supply to one memory cell via a power supply node, to store data; providing write data to the one memory cell via a bitline in a write operation; and discharging, selectively based on the write data, the power supply node to the bitline.

Abstract: A light emitting diode structure including a substrate, a first type doped semiconductor layer, an insulating layer, light emitting layers, a second type doped semiconductor layer, a first pad and a second pad is provided. The first type doped semiconductor layer is disposed on the substrate. The insulating layer having openings is disposed on the first type doped semiconductor layer for exposing a part of the first type doped semiconductor layer. The light emitting layers are disposed within the corresponding openings of the insulating layer respectively. The second type doped semiconductor layer is disposed on the insulating layer and the light emitting layers. The first pad is disposed on the first type doped semiconductor layer and is electrically connected thereto. The second pad is disposed on the second type doped semiconductor layer and is electrically connected thereto. Besides, air gaps may also be utilized for separating the light emitting layers.

Abstract: A method of forming a gate structure includes forming sequentially a pad layer and a first photoresist layer over a substrate. A cross-linked surface layer is formed on the surface of the first photoresist layer, followed by rounding the profile of the first photoresist layer, and removing the exposed pad layer to expose the substrate. A second photoresist layer is formed over the first photoresist layer, wherein a portion of the first photoresist layer and the exposed substrate are exposed by the second photoresist layer. Thereafter, a conductive layer is formed, wherein the conductive layer formed on the second photoresist layer is separated from the conductive layer formed on the first photoresist layer and the exposed substrate. The first and the second photoresist layers are removed while the conductive layer on the second photoresist layer is concurrently being striped. The remaining conductive layer serves as a gate structure.