Abstract: Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor in which a pixel sensor spans multiple integrated circuit (IC) chips and is devoid of a shallow trench isolation (STI) structure at a photodetector of the pixel sensor. The photodetector and a first transistor form a first portion of the pixel sensor at a first IC chip. A plurality of second transistors forms a second portion of the pixel sensor at a second IC chip. By omitting the STI structure at the photodetector, a doped well surrounding and demarcating the pixel sensor may have a lesser width than it would otherwise have. Hence, the doped well may consume less area of the photodetector. This, in turn, allows enhanced scaling down of the pixel sensor.

Abstract: An eye center localization method includes performing an image sketching step, a frontal face generating step, an eye center marking step and a geometric transforming step. The image sketching step is performed to drive a processing unit to sketch a face image from the image. The frontal face generating step is performed to drive the processing unit to transform the face image into a frontal face image according to a frontal face generating model. The eye center marking step is performed to drive the processing unit to mark a frontal eye center position information on the frontal face image. The geometric transforming step is performed to drive the processing unit to calculate two rotating variables between the face image and the frontal face image, and calculate the eye center position information according to the two rotating variables and the frontal eye center position information.

Abstract: An eye center localization method includes performing an image sketching step, a frontal face generating step, an eye center marking step and a geometric transforming step. The image sketching step is performed to drive a processing unit to sketch a face image from the image. The frontal face generating step is performed to drive the processing unit to transform the face image into a frontal face image according to a frontal face generating model. The eye center marking step is performed to drive the processing unit to mark a frontal eye center position information on the frontal face image. The geometric transforming step is performed to drive the processing unit to calculate two rotating variables between the face image and the frontal face image, and calculate the eye center position information according to the two rotating variables and the frontal eye center position information.

Abstract: An image grid line removing method is used for removing grid lines of an image and includes a Fourier transform step, a Gaussian-like masking step and an inverse Fourier transform step. The Fourier transform step is for providing a Fourier transform to process the image to generate a frequency domain image. The Gaussian-like masking step is for providing a Gaussian-like masking model to process the frequency domain image to generate a frequency domain masked image. The inverse Fourier transform step is for providing an inverse Fourier transform to process the frequency domain masked image to generate a grid line removing image.

Abstract: An electronic device may have a display. The display has pixels configured to display an image. The display is mounted in a housing. The housing may include head-mounted support structures configured to support the display for viewing through lenses. The pixels of the display may be covered by a layer of thin-film encapsulation. The thin-film encapsulation may be covered with a cover layer such as a glass cover layer that is attached to the thin-film encapsulation layer by a layer of adhesive. To suppress internal light reflections, the display may include reflection suppression structures. The reflection suppression structures may include an antireflection layer and/or polarizer and waveplate layers. The reflection suppression structures may be formed on an outwardly facing surface of the cover layer and/or between the thin-film encapsulation layer and the cover layer.

Abstract: An image grid line removing method is used for removing grid lines of an image and includes a Fourier transform step, a Gaussian-like masking step and an inverse Fourier transform step. The Fourier transform step is for providing a Fourier transform to process the image to generate a frequency domain image. The Gaussian-like masking step is for providing a Gaussian-like masking model to process the frequency domain image to generate a frequency domain masked image. The inverse Fourier transform step is for providing an inverse Fourier transform to process the frequency domain masked image to generate a grid line removing image.

Abstract: A PLL apparatus and system for generating distributed clocks are disclosed. A synchronizing-edge detector is provided to the PLL apparatus in the PLL system to detect synchronizing edges of the input and output clock signals having gear relationship for the PLL apparatus. The synchronizing-edge detector detects a sample signal the frequency of which is the common divisor of the frequencies of the input and output signal. The PLL apparatus may be provided with a detection terminal connected with one of the input terminals of a pre-divider and loop divider for outputting the sample signal. Alternatively, the PLL system can comprise at least one additional divider coupled to the input and/or output signals of a PLL apparatus to generate the sample signal.

Abstract: A PLL apparatus and system for generating distributed clocks are disclosed. A synchronizing-edge detector is provided to the PLL apparatus in the PLL system to detect synchronizing edges of the input and output clock signals having gear relationship for the PLL apparatus. The synchronizing-edge detector detects a sample signal the frequency of which is the common divisor of the frequencies of the input and output signal. The PLL apparatus may be provided with a detection terminal connected with one of the input terminals of a pre-divider and loop divider for outputting the sample signal. Alternatively, the PLL system can comprise at least one additional divider coupled to the input and/or output signals of a PLL apparatus to generate the sample signal.

Abstract: A multiply accumulator performs a multiplication-and-addition operation for a first multiplier with N bits, a second multiplier with N bits, and an addend with M bits, wherein M is larger than 2N. The multiply accumulator includes a modified Booth encoder and a multiplication-and-addition unit. The modified Booth encoder performs a Booth encoding to either the first multiplier or its bit inversion by supplementing a multiplier sign bit behind a least significant bit of either the first multiplier or its bit inversion. The multiplication-and-addition unit includes a carry save adder tree and a sign extension adder and achieves a high speed of the multiplication-and-addition operation by simultaneously performing the multiplication and addition.

Abstract: A frequency divider with a 50% duty cycle. The present invention includes a divider, a counter, a first comparator, a second comparator, a first flip-flop, an AND gate, a second flip-flip, and an OR gate for generating odd divided frequencies and even divided frequencies having 50% duty cycles using a single circuit.

Abstract: A multiply accumulator performs a multiplication-and-addition operation for a first multiplier with N bits, a second multiplier with N bits, and an addend with M bits, wherein M is larger than 2N. The multiply accumulator includes a modified Booth encoder and a multiplication-and-addition unit. The modified Booth encoder performs a Booth encoding to either the first multiplier or its bit inversion by supplementing a multiplier sign bit behind a least significant bit of either the first multiplier or its bit inversion. The multiplication-and-addition unit includes a carry save adder tree and a sign extension adder and achieves a high speed of the multiplication-and-addition operation by simultaneously performing the multiplication and addition.