Patents by Inventor Chi-Jung Lin

Chi-Jung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240133918
    Abstract: In a method for obtaining the equivalent oxide thickness of a dielectric layer, a first semiconductor capacitor including a first silicon dioxide layer and a second semiconductor capacitor including a second silicon dioxide layer are provided and a modulation voltage is applied to the semiconductor capacitors to measure a first scanning capacitance microscopic signal and a second scanning capacitance microscopic signal. According to the equivalent oxide thicknesses of the silicon dioxide layers and the scanning capacitance microscopic signals, an impedance ratio is calculated. The modulation voltage is applied to a third semiconductor capacitor including a dielectric layer to measure a third scanning capacitance microscopic signal. Finally, the equivalent oxide thickness of the dielectric layer is obtained according to the equivalent oxide thickness of the first silicon dioxide layer, the first scanning capacitance microscopic signal, third scanning capacitance microscopic signal, and the impedance ratio.
    Type: Application
    Filed: April 12, 2023
    Publication date: April 25, 2024
    Inventors: MAO-NAN CHANG, CHI-LUN LIU, HSUEH-LIANG CHOU, YI-SHAN WU, CHIAO-JUNG LIN, YU-HSUN HSUEH
  • Publication number: 20220259868
    Abstract: A flooring panel (50) is provided with a quick-release adhesive sheet (10) such that the flooring panel (50) can be quickly attached to a support surface and removed therefrom. More particularly, the flooring panel (50) includes a top floor layer (52) attached or laminated to the adhesive sheet (10), which underlies the floor layer (52). The top flooring layer (52) can be any type of flooring material, such as vinyl flooring, real or engineered wood flooring, etc. (FIG. 8).
    Type: Application
    Filed: February 28, 2022
    Publication date: August 18, 2022
    Applicants: EcoInteriors Corp., OneFlor USA, LLC
    Inventors: David J. Kim, Chi-Jung Lin
  • Publication number: 20200378133
    Abstract: A flooring panel (50) is provided with a quick-release adhesive sheet (10) such that the flooring panel (50) can be quickly attached to a support surface and removed therefrom. More particularly, the flooring panel (50) includes a top floor layer (52) attached or laminated to the adhesive sheet (10), which underlies the floor layer (52). The top flooring layer (52) can be any type of flooring material, such as vinyl flooring, real or engineered wood flooring, etc. (FIG. 8).
    Type: Application
    Filed: February 11, 2020
    Publication date: December 3, 2020
    Applicant: EcoInteriors Corp.
    Inventors: David J. Kim, Chi-Jung Lin
  • Patent number: 10753100
    Abstract: A flooring panel is provided with a quick-release adhesive sheet such that the flooring panel can be quickly attached to a support surface and removed therefrom. More particularly, the flooring panel includes a top floor layer attached or laminated to the adhesive sheet, which underlies the floor layer. The top flooring layer can be any type of flooring material, such as vinyl flooring, real or engineered wood flooring, etc.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 25, 2020
    Assignee: Ecointeriors Corp.
    Inventors: David J. Kim, Chi-Jung Lin
  • Publication number: 20190048593
    Abstract: A flooring panel is provided with a quick-release adhesive sheet such that the flooring panel can be quickly attached to a support surface and removed therefrom. More particularly, the flooring panel includes a top floor layer attached or laminated to the adhesive sheet, which underlies the floor layer. The top flooring layer can be any type of flooring material, such as vinyl flooring, real or engineered wood flooring, etc.
    Type: Application
    Filed: March 22, 2018
    Publication date: February 14, 2019
    Inventors: David J. Kim, Chi-Jung Lin
  • Patent number: 10055366
    Abstract: A method for data transmission within a server that includes a processor, a main memory, a southbridge, a chipset, and a buffer, the chipset including a baseboard management controller (BMC), the method including: obtaining memory information about a segment of the peripheral memory allocated for a peripheral controller included in the chipset; transmitting a notifying command to the BMC indicating a data size of to-be-transmitted data associated with a booting operation of the server; transmitting at least a part of the to-be-transmitted data to the segment, according to the memory information; and transmitting a standby command to the BMC indicating that the part of the to-be-transmitted data has been stored in the segment.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 21, 2018
    Assignee: Mitac Computing Technology Corporation
    Inventors: Chi-Jung Lin, Chi-Hao Kuan, Hsiang-Jui Huang
  • Publication number: 20170262388
    Abstract: A method for data transmission within a server that includes a processor, a main memory, a southbridge, a chipset, and a buffer, the chipset including a baseboard management controller (BMC), the method including: obtaining memory information about a segment of the peripheral memory allocated for a peripheral controller included in the chipset; transmitting a notifying command to the BMC indicating a data size of to-be-transmitted data associated with a booting operation of the server; transmitting at least a part of the to-be-transmitted data to the segment, according to the memory information; and transmitting a standby command to the BMC indicating that the part of the to-be-transmitted data has been stored in the segment.
    Type: Application
    Filed: March 1, 2017
    Publication date: September 14, 2017
    Inventors: Chi-Jung LIN, Chi-Hao KUAN, Hsiang-Jui HUANG
  • Publication number: 20160326750
    Abstract: A floor tile structure includes a surface layer, an intermediate layer mounted on a bottom face of the surface layer, and a bottom layer arranged on a bottom face of the intermediate layer and stuck to the surface layer. The intermediate layer includes an adhesive that is applied over the bottom face of the surface layer. The bottom layer includes a film layer attached to the bottom face of the intermediate layer, a reusable sticky layer attached to a bottom face of the film layer and a release paper attached to a bottom face of the reusable sticky layer. The reusable sticky layer can be used and stuck repeatedly. The release paper can be removed from the reusable sticky layer.
    Type: Application
    Filed: October 19, 2015
    Publication date: November 10, 2016
    Inventor: Chi-Jung Lin
  • Patent number: 6333261
    Abstract: A semiconductor wafer includes a substrate, an aluminum layer on the substrate, an anti-reflection coating on the aluminum layer, a dielectric layer on the anti-reflection coating, and a via hole that passes through the dielectric layer and the anti-reflection coating down to a predetermined depth within the aluminum layer. A titanium layer is formed on the bottom and on the walls of the via hole. A physical vapor deposition process is then performed to form a first titanium nitride layer on the titanium layer. A chemical vapor deposition process is then performed to form a second titanium nitride layer on the first titanium nitride layer.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: December 25, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Jung Lin, Jyh-J Huang, Horng-Bor Lu, Kun-Lin Wu