Abstract: A semiconductor package and manufacturing method is disclosed. The semiconductor package includes a semiconductor chip having a plurality of chip terminals formed on one surface thereof, a redistribution layer electrically connected to the chip terminal and extending outwardly from a side surface of the chip to electrically connect the chip terminal to an external device, an external pad provided on the insulating layer, formed to be in contact with the redistribution layer exposed from the insulating layer to be electrically connected to the redistribution layer, and exposed to an upper side of the insulating layer; an external connection terminal formed on the external pad and contacting an external device, a protective layer formed to surround at least one surface and a side surface of the chip, and an insulating layer formed to cover the redistribution layer.

Abstract: There is provided a bump structure for a semiconductor device, comprising a metal post formed on and electrically connected to an electrode pad on a substrate, a solder post formed on the top surface of the metal post, said solder post having the same horizontal width as the metal post and the top surface of the solder post being substantially rounded, and an intermetallic compound layer disposed at the interface between the metal post and the solder post. An oxide layer formed on the solder post prevents solder post under reflow from being changed into a spherical shape. An intermetallic compound layer may be formed by an aging process at the interface between the metal post and the solder post. The bump structure can realize fine pitch semiconductor package without a short between neighboring bumps.

Abstract: There is provided a bump structure for a semiconductor device, comprising a metal post formed on and electrically connected to an electrode pad on a substrate, a solder post formed on the top surface of the metal post, said solder post having the same horizontal width as the metal post and the top surface of the solder post being substantially rounded, and an intermetallic compound layer disposed at the interface between the metal post and the solder post. An oxide layer formed on the solder post prevents solder post under reflow from being changed into a spherical shape. An intermetallic compound layer may be formed by an aging process at the interface between the metal post and the solder post. The bump structure can realize fine pitch semiconductor package without a short between neighboring bumps.

Abstract: A package for semiconductor image pickup device is provided. The package is fabricated by using flip chip bumping. During deposition process of forming a metallic bonding layer and a metal layer for plating, a surface of a semiconductor image pickup device is maintained at the range between room temperature and 200° C. in accordance with a first embodiment. A polymer layer for preventing stress from generating can absorb stress generated during the deposition process in accordance with a second embodiment. According to the present invention, a functional polymer layer on the surface of a semiconductor image pickup device can be prevent from being deteriorated in its properties and from transforming at its surface.

Abstract: A package for semiconductor image pickup device is provided. The package is fabricated by using flip chip bumping. During deposition process of forming a metallic bonding layer and a metal layer for plating, a surface of a semiconductor image pickup device is maintained at the range between room temperature and 200° C. in accordance with a first embodiment. A polymer layer for preventing stress from generating can absorb stress generated during the deposition process in accordance with a second embodiment. According to the present invention, a functional polymer layer on the surface of a semiconductor image pickup device can be prevent from being deteriorated in its properties and from transforming at its surface.

Abstract: An area array type semiconductor package includes a plurality of conductive media such as solder bumps or solder balls, attached to respective bond pads of a chip. The conductive media act as external output terminals. The chip is attached to a lead frame by a thermal conductive adhesive, and a predetermined area of the lead frame and the semiconductor chip are packaged with a molding resin. Leads of the lead frame are then trimmed and formed so that the lead frame, to which the semiconductor chip is adhered, acts as a heat sink. This allows the package to be used for a high-powered semiconductor device which radiates a high temperature heat. Also, because conductive media such as solder bumps or solder balls can be used to directly connect bond pads of the chip to conductive regions of a circuit board, a size of the semiconductor package can be minimized, the arrangement of the bonding pads on the chip can be easily planned, and electrical characteristics of the semiconductor package can be improved.

Abstract: A land grid array (LGA) type semiconductor chip package includes an insulation body having a plurality of first conductive interconnections embedded therein. A cavity is formed in an upper portion of the insulation body. A plurality of first conductive interconnection patterns is formed outside the cavity and on marginal upper surfaces of the insulation body, and a plurality of second conductive interconnection patterns is formed on marginal lower surfaces of the insulation body. A plurality of third conductive interconnection patterns electrically connects the first and second conductive interconnection patterns, and a plurality of conductive bond pads is formed on a bottom of the cavity. A semiconductor chip is attached on the respective bond pads by a first adhesive member and a heat discharge member is attached by a second adhesive member on an upper surface of the semiconductor chip. An epoxy molding compound fills the cavity.

Abstract: An encapsulation method for a ball grid array (BGA) semiconductor package, includes: adhering one sided adhesive tape to an upper portion of the semiconductor package after performing a wire bonding; carrying out a molding by using a mold having a groove of a certain size inside; and removing the one side adhesive tape after completing the molding, whereby a flash is prevented from occurring during the BGA encapsulation process.

Abstract: A land grid array (LGA) type semiconductor chip package includes an insulation body having a plurality of first conductive interconnections embedded therein. A cavity is formed in an upper portion of the insulation body. A plurality of first conductive interconnection patterns is formed outside the cavity and on marginal upper surfaces of the insulation body, and a plurality of second conductive interconnection patterns is formed on marginal lower surfaces of the insulation body. A plurality of third conductive interconnection patterns electrically connects the first and second conductive interconnection patterns, and a plurality of conductive bond pads is formed on a bottom of the cavity. A semiconductor chip is attached on the respective bond pads by a first adhesive member and a heat discharge member is attached by a second adhesive member on an upper surface of the semiconductor chip. An epoxy molding compound fills the cavity.

Abstract: An encapsulation method for a ball grid array (BGA) semiconductor package, includes: adhering one sided adhesive tape to an upper portion of the semiconductor package after performing a wire bonding; carrying out a molding by using a mold having a groove of a certain size inside; and removing the one side adhesive tape after completing the molding, whereby a flash is prevented from occurring during the BGA encapsulation process.

Abstract: A land grid array (LGA) type semiconductor chip package includes an insulation body having a plurality of first conductive interconnections embedded therein. A cavity is formed in an upper portion of the insulation body. A plurality of first conductive interconnection patterns is formed outside the cavity and on marginal upper surfaces of the insulation body, and a plurality of second conductive interconnection patterns is formed on marginal lower surfaces of the insulation body. A plurality of third conductive interconnection patterns electrically connects the first and second conductive interconnection patterns, and a plurality of conductive bond pads is formed on a bottom of the cavity. A semiconductor chip is attached on the respective bond pads by a first adhesive member and a heat discharge member is attached by a second adhesive member on an upper surface of the semiconductor chip. An epoxy molding compound fills the cavity.

Abstract: An area array type semiconductor package includes a plurality of conductive media, such as solder bumps or solder balls, attached to respective bond pads of a chip. The conductive media act as external output terminals. The chip is attached to a lead frame by a thermal conductive adhesive, and a predetermined area of the lead frame and the semiconductor chip are packaged with a molding resin. Leads of the lead frame are then trimmed and formed so that the lead frame, to which the semiconductor chip is adhered, acts as a heat sink. This allows the package to be used for a high-powered semiconductor device which radiates a high temperature heat. Also, because conductive media such as solder bumps or solder balls can be used to directly connect bond pads of the chip to conductive regions of a circuit board, a size of the semiconductor package can be minimized, the arrangement of the bonding pads on the chip can be easily planned, and electrical characteristics of the semiconductor package can be improved.

Abstract: An area array type semiconductor package includes a plurality of conductive media, such as solder bumps or solder balls, attached to respective bond pads of a chip. The conductive media act as external output terminals. The chip is attached to a lead frame by a thermal conductive adhesive, and a predetermined area of the lead frame and the semiconductor chip are packaged with a molding resin. Leads of the lead frame are then trimmed and formed so that the lead frame, to which the semiconductor chip is adhered, acts as a heat sink. This allows the package to be used for a high-powered semiconductor device which radiates a high temperature heat. Also, because conductive media such as solder bumps or solder balls can be used to directly connect bond pads of the chip to conductive regions of a circuit board, a size of the semiconductor package can be minimized, the arrangement of the bonding pads on the chip can be easily planned, and electrical characteristics of the semiconductor package can be improved.

Abstract: A package for housing an electronic device without the use of wire bonds includes a package body with a first cavity formed in its top surface, and a second cavity formed in a bottom surface of the first cavity. A plurality of signal lines in the package body connect the bottom surface of the second cavity to the bottom surface of the package body. A semiconductor chip package incorporating the package of the present invention further includes a semiconductor chip mounted in the package body. Bonding pads on the semiconductor chip are connected to the signal lines on the bottom surface of the second cavity via electrically conductive bumps.

Abstract: A semiconductor chip stack package includes a plurality of semiconductor chips, each having a plurality of chip pads formed on an upper surface and a plurality of wires respectively coupling a corresponding one of the plurality of chip pads to an edge portion of the semiconductor chip. A package body is formed by stacking the plurality of semiconductor chips one over another using a first adhesive medium. A tab tape attaches to a second side surface of the package body using a third adhesive medium. A heat sink attaches to each of a lower, upper and first side surfaces of the package body using a second adhesive medium. Then, a plurality of solder balls is formed on a lower surface of the tab tape for coupling to an external medium, such as a printed circuit board. The stack package facilitates external emission of the heat generated by the semiconductor chips to prevent the stack package reliability from deterioration.

Abstract: A semiconductor package includes a semiconductor chip having a plurality of bonding pads, and a plurality of wire contacts; a plurality of leads; a plurality or wires, and a resin molded over the majority of the package. The leads have substrate connecting portions and wire connecting portions. A first side of the substrate connecting portions of the leads connects to the bonding pads on the semiconductor chip. Second sides of the substrate connecting portions of the leads are exposed, i.e., they are not covered with the molding resin. The wires are connected between the wire connecting portions of the leads and the wire contacts on the semiconductor chip. The wire connecting portion of at least one of the leads may be split into at least two branches. In addition, grooves may be formed on the exposed portions of the substrate connecting portions of the leads so that the grooves are engageable with corresponding projections on a device upon which the semiconductor package will be mounted.

Abstract: An improved package is thinner with increased memory capacity and improved heat emission effect. The package includes a plurality of leads, where each lead comprises a first connection lead and a second connection lead with upper and lower surfaces. An integrated chip, such as a semiconductor chip, is attached to a portion of the upper surface of the first connection lead. The chip and leads are molded such that the lower surface of the first connection leads and upper surface of the second connection leads are exposed.