Abstract: A method of manufacturing a non-volatile memory is provided. A substrate including a first region and a second region is provided. A first patterning process is performed to the first region, so as to form a plurality of gate stack structures in the first region. Afterwards, a first sidewall oxide layer is formed to cover sidewalls and an upper surface of each gate stack structure, and a protection layer is then formed on the first sidewall oxide layer. Next, an ion implantation process is performed to the second region, and a second patterning process is performed to the second region so as to form a plurality of gate structures. Then, a second sidewall oxide layer covering sidewalls of each gate structure is formed.

Abstract: A manufacturing method of floating gate is disclosed. A substrate having a plurality of isolation structures is provided, and top surfaces of the isolation structures are higher than a top surface of the substrate. A first conductive layer is formed on the substrate. A sacrificial layer is formed on the first conductive layer. Parts of the sacrificial layer are removed while parts of the sacrificial layer on the first conductive layer between the isolation structures are remained. Parts of the first conductive layer are removed by using the remaining parts of the sacrificial layer as masks to form conductive structures between the adjacent isolation structures. The remaining parts of the sacrificial layer are removed. A second conductive layer is formed on the substrate and the second conductive layer electrically connects with the conductive structures. The second conductive layer and the conductive structures are patterned to form floating gates.

Abstract: A method of manufacturing a non-volatile memory is provided. A substrate including a first region and a second region is provided. A first patterning process is performed to the first region, so as to form a plurality of gate stack structures in the first region. Afterwards, a first sidewall oxide layer is formed to cover sidewalls and an upper surface of each gate stack structure, and a protection layer is then formed on the first sidewall oxide layer. Next, an ion implantation process is performed to the second region, and a second patterning process is performed to the second region so as to form a plurality of gate structures. Then, a second sidewall oxide layer covering sidewalls of each gate structure is formed.