Patents by Inventor Chi-Kai Hsieh
Chi-Kai Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11964881Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.Type: GrantFiled: July 27, 2020Date of Patent: April 23, 2024Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Pu-Wei Wu, Yi-Chieh Hsieh, Han-Yi Wang, Kuang-Chih Tso, Tzu-Ying Chan, Chung-Kai Chang, Chi-Shih Chen, Yu-Ting Cheng
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Publication number: 20240120812Abstract: An integrated motor and drive assembly is disclosed and includes a housing, a motor and a drive. The housing includes a motor-accommodation portion and a drive-accommodation portion. The drive includes a power board and a control board. The power board is made of a high thermal conductivity substrate and includes a power element and an encoder disposed on the first side, the first side faces the motor, the power board and the motor are stacked along a first direction, and the second side contacts the housing to from a heat-dissipating route. The control board is disposed adjacent to the power board. The control board and the power board are arranged along a second direction perpendicular to the first direction, and the first direction is parallel to an axial direction of the motor. A part of the power board and a part of the control board are directly contacted to form an electrical connection.Type: ApplicationFiled: July 17, 2023Publication date: April 11, 2024Inventors: Chi-Hsiang Kuo, Yi-Yu Lee, Zuo-Ying Wei, Yuan-Kai Liao, Wen-Cheng Hsieh
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Publication number: 20240098754Abstract: Various solutions for providing a unified control channel framework in mobile communications are described. An apparatus receives a first-stage downlink control information (DCI) from a network node. The first-stage DCI indicates first scheduling information associated with a second-stage DCI. Then, the apparatus receives the second-stage DCI from the network node according to the first scheduling information. The second-stage DCI indicates second scheduling information associated with one or more carriers or cells or indicates non-scheduling information associated with one or more features. Also, the apparatus performs operations including either one of the following: (1) performing a PDSCH reception or a PUSCH transmission on at least one of the one or more carriers or cells according to the second scheduling information; and (2) applying the non-scheduling information in an event that the apparatus supports at least one of the one or more features.Type: ApplicationFiled: August 15, 2023Publication date: March 21, 2024Inventors: Yi-Ju Liao, Pei-Kai Liao, Chi-Hsuan Hsieh
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Patent number: 9934845Abstract: A semiconductor device comprising a first supply voltage, a second supply voltage, different from the first supply voltage; and a switching circuit. The switching circuit comprises an input configured to receive an input signal corresponding to the first supply voltage and an output configured to output an output signal corresponding to the second supply voltage. The switching circuit is a combined latch with a built-in level shifter that provides latching functionality and level shifting functionality and a leakage path is cut-off when the switching circuit is providing latching functionality.Type: GrantFiled: January 13, 2017Date of Patent: April 3, 2018Assignee: Taiwan Semiconductor Manufacturing Campany LimitedInventors: Hao-I Yang, Cheng Hung Lee, Chi-Kai Hsieh, Fu-An Wu, Tsung-Hsien Huang
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Patent number: 9934828Abstract: Systems and methods are provided for a sense amplifier/write driver circuit. A system includes a set of transistors responsive to a memory cell, the set of transistors configured to operate as a sense amplifier in a first mode and to operate as a write driver in a second mode. One or more switches are configured to switch the set of transistors from the first mode to the second mode based on a control signal. Particular transistors of the set of transistors are configured by the one or more switches to amplify and retain data at a pair of input/output nodes for a period of time in the first mode. The particular transistors are further configured by the one or more switches to drive data to the pair of input/output nodes in the second mode.Type: GrantFiled: January 25, 2017Date of Patent: April 3, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chi-Kai Hsieh, Cheng Hung Lee, Fu-An Wu
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Publication number: 20170345487Abstract: A semiconductor device comprising a first supply voltage, a second supply voltage, different from the first supply voltage; and a switching circuit. The switching circuit comprises an input configured to receive an input signal corresponding to the first supply voltage and an output configured to output an output signal corresponding to the second supply voltage. The switching circuit is a combined latch with a built-in level shifter that provides latching functionality and level shifting functionality and a leakage path is cut-off when the switching circuit is providing latching functionality.Type: ApplicationFiled: January 13, 2017Publication date: November 30, 2017Inventors: Hao-I Yang, Cheng Hung Lee, Chi-Kai Hsieh, Fu-An Wu, Tsung-Hsien Huang
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Publication number: 20170345465Abstract: Systems and methods are provided for a sense amplifier/write driver circuit. A system includes a set of transistors responsive to a memory cell, the set of transistors configured to operate as a sense amplifier in a first mode and to operate as a write driver in a second mode. One or more switches are configured to switch the set of transistors from the first mode to the second mode based on a control signal. Particular transistors of the set of transistors are configured by the one or more switches to amplify and retain data at a pair of input/output nodes for a period of time in the first mode. The particular transistors are further configured by the one or more switches to drive data to the pair of input/output nodes in the second mode.Type: ApplicationFiled: January 25, 2017Publication date: November 30, 2017Inventors: Chi-Kai Hsieh, Cheng Hung Lee, Fu-An Wu
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Patent number: 9679619Abstract: A sense amplifier includes a cross latch, a first pass gate, a second pass gate, a first data line, a second data line, a first circuit, and a second circuit. The cross latch has a first input/output (I/O) node and a second I/O node. The first pass gate is coupled between the first data line and the first I/O node. The second pass gate is coupled between the second data line and the second I/O node. The first circuit is coupled with the first I/O node and the second data line. The second circuit is coupled with the second I/O node and the first data line. The first circuit is configured to be turned off when the second data line has a first logical value and to be at least lightly turned on when the second data line has a voltage level between the first logical value and a second logical value different from the first logical value.Type: GrantFiled: March 14, 2014Date of Patent: June 13, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Kai Hsieh, Hong-Chen Cheng, Cheng Hung Lee
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Patent number: 8970256Abstract: The present disclosure relates to a differential sense amplifier comprising first and second cross-coupled inverters with first and second complimentary storage nodes. A first current control element changes a current through the first cross-coupled inverter based upon an output of a second cross-coupled inverter, and a second current control element changes a current through the second cross-coupled inverter based upon an output of the first cross-coupled inverter. Other devices and methods are also disclosed.Type: GrantFiled: May 7, 2013Date of Patent: March 3, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng Hung Lee, Hektor Huang, Chi-Kai Hsieh, Shi-Wei Chang, Hong-Chen Cheng
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Publication number: 20140269128Abstract: A sense amplifier includes a cross latch, a first pass gate, a second pass gate, a first data line, a second data line, a first circuit, and a second circuit. The cross latch has a first input/output (I/O) node and a second I/O node. The first pass gate is coupled between the first data line and the first I/O node. The second pass gate is coupled between the second data line and the second I/O node. The first circuit is coupled with the first I/O node and the second data line. The second circuit is coupled with the second I/O node and the first data line. The first circuit is configured to be turned off when the second data line has a first logical value and to be at least lightly turned on when the second data line has a voltage level between the first logical value and a second logical value different from the first logical value.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Kai HSIEH, Hong-Chen CHENG, Cheng Hung LEE
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Publication number: 20140266436Abstract: The present disclosure relates to a differential sense amplifier comprising first and second cross-coupled inverters with first and second complimentary storage nodes. A first current control element changes a current through the first cross-coupled inverter based upon an output of a second cross-coupled inverter, and a second current control element changes a current through the second cross-coupled inverter based upon an output of the first cross-coupled inverter. Other devices and methods are also disclosed.Type: ApplicationFiled: May 7, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng Hung Lee, Hektor Huang, Chi-Kai Hsieh, Shi-Wei Chang, Hong-Chen Cheng